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Travelled to:
1 × Korea
2 × France
Collaborated with:
J.Schönherr W.Vermeiren G.Elst T.Klotz N.Seßler E.Fordran K.Turek
Talks about:
algorithm (1) transfer (1) descript (1) suggest (1) equival (1) circuit (1) automat (1) acceler (1) system (1) regist (1)

Person: Bernd Straube

DBLP DBLP: Straube:Bernd

Contributed to:

CASE 20122012
DATE 20002000
EDAC-ETC-EUROASIC 19941994

Wrote 3 papers:

CASE-2012-KlotzSSFTS #on the #verification
On the formal verification of routing in material handling systems (TK, NS, BS, EF, KT, JS), pp. 8–13.
DATE-2000-SchonherrS #algorithm #automation #equivalence
Automatic Equivalence Check of Circuit Descriptions at Clocked Algorithmic and Register Transfer Level (JS, BS), p. 759.
EDAC-1994-VermeirenSE #fault #simulation
A Suggestion for Accelerating the Analog Fault Simulation (WV, BS, GE), p. 662.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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