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Travelled to:
1 × France
1 × Germany
Collaborated with:
P.Daglio D.Iezzi D.Rimondi S.Santapa
Talks about:
technolog (1) hierarchi (1) volatil (1) qualifi (1) parasit (1) netlist (1) signal (1) memori (1) layout (1) design (1)

Person: Carlo Roma

DBLP DBLP: Roma:Carlo

Contributed to:

DATE DF 20042004
DATE 20032003

Wrote 2 papers:

DATE-DF-2004-DaglioIRRS #component #performance #simulation
Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic Components (PD, DI, DR, CR, SS), pp. 336–337.
DATE-2003-DaglioR #bottom-up #design #top-down
A Fully Qualified Top-Down and Bottom-Up Mixed-Signal Design Flow for Non Volatile Memories Technologies (PD, CR), pp. 20274–20279.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.