Travelled to:1 × France
1 × Germany
Collaborated with:P.Daglio D.Iezzi D.Rimondi S.Santapa
Talks about:technolog (1) hierarchi (1) volatil (1) qualifi (1) parasit (1) netlist (1) signal (1) memori (1) layout (1) design (1)
Person: Carlo Roma
DBLP: Roma:Carlo
Contributed to:
20042003Wrote 2 papers:
- DATE-DF-2004-DaglioIRRS #component #performance #simulation
- Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic Components (PD, DI, DR, CR, SS), pp. 336–337.
- DATE-2003-DaglioR #bottom-up #design #top-down
- A Fully Qualified Top-Down and Bottom-Up Mixed-Signal Design Flow for Non Volatile Memories Technologies (PD, CR), pp. 20274–20279.