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Travelled to:
1 × France
1 × Germany
1 × USA
Collaborated with:
M.Pedram L.Chen C.Ding Q.Wu G.Mehta F.Rastgar
Talks about:
power (4) dissip (2) microprocessor (1) architectur (1) distribut (1) synthesi (1) function (1) statist (1) program (1) cirucit (1)

Person: Cheng-Ta Hsieh

DBLP DBLP: Hsieh:Cheng=Ta

Contributed to:

DATE 20012001
DATE 20002000
DAC 19971997

Wrote 4 papers:

DATE-2001-HsiehCP #analysis #simulation
Microprocessor power analysis by labeled simulation (CTH, LC, MP), pp. 182–189.
DATE-2000-HsiehP #architecture #optimisation
Architectural Power Optimization by Bus Splitting (CTH, MP), pp. 612–616.
DAC-1997-DingWHP #cumulative #estimation #statistics
Statistical Estimation of the Cumulative Distribution Function for Power Dissipation in VLSI Cirucits (CSD, QW, CTH, MP), pp. 371–376.
DAC-1997-HsiehPMR #evaluation #synthesis
Profile-Driven Program Synthesis for Evaluation of System Power Dissipation (CTH, MP, GM, FR), pp. 576–581.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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