Travelled to:2 × USA
Collaborated with:J.Lin C.Huang S.Chang Y.Chiu
Talks about:placement (2) consid (2) analog (2) constraint (1) capacitor (1) systemat (1) mismatch (1) centroid (1) boundari (1) perform (1)
Person: Cheng-Wu Lin
DBLP: Lin:Cheng=Wu
Contributed to:
20112010Wrote 2 papers:
- DAC-2011-LinLCHC #random
- Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits (CWL, JML, YCC, CPH, SJC), pp. 528–533.
- DAC-2010-LinLHC #bound #constraints
- Performance-driven analog placement considering boundary constraint (CWL, JML, CPH, SJC), pp. 292–297.