Travelled to:1 × Germany
2 × USA
Collaborated with:T.Chang ∅ J.Li T.Tseng J.Ding
Talks about:design (2) yield (2) plas (2) playground (1) transpar (1) programm (1) consider (1) diagnos (1) scheme (1) repair (1)
Person: Chin-Long Wey
DBLP: Wey:Chin=Long
Contributed to:
2005
199019881987Wrote 4 papers:
- DATE-2005-LiTW #embedded #performance
- An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories (JFL, TWT, CLW), pp. 574–579.
- DAC-1990-WeyDC #design
- Design of Repairable and Fully Diagnosable Folded PLAs for Yield Enhancement (CLW, JD, TYC), pp. 327–332.
- DAC-1988-WeyC #named
- PLAYGROUND: Minimization of PLAs with Mixed Ground True Outputs (CLW, TYC), pp. 421–426.
- DAC-1987-Wey #array #design #logic #on the #programmable
- On Yield Consideration for the Design of Redundant Programmable Logic Arrays (CLW), pp. 622–628.