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Travelled to:
1 × France
2 × Germany
3 × USA
Collaborated with:
D.F.Wong J.Zeng N.Menezes S.Huang S.Hung Y.Chang Y.Chen
Talks about:
interconnect (3) optim (3) wire (3) size (3) model (2) delay (2) base (2) use (2) lagrangian (1) transform (1)

Person: Chung-Ping Chen

DBLP DBLP: Chen:Chung=Ping

Contributed to:

DATE 20152015
DATE 20102010
DATE 20082008
DAC 19991999
DAC 19971997
DAC 19961996

Wrote 8 papers:

DATE-2015-HuangHC #algorithm #clustering #framework #multi #problem #scalability
Clustering-based multi-touch algorithm framework for the tracking problem with a large number of points (SLH, SYH, CPC), pp. 719–724.
DATE-2010-ZengC #metric #using
Interconnect delay and slew metrics using the beta distribution (JKZ, CPC), pp. 1329–1332.
DATE-2008-ZengC #analysis #polynomial #random
Deep Submicron Interconnect Timing Model with Quadratic Random Variable Analysis (JKZ, CPC), pp. 1091–1094.
DAC-1999-ChenM #using
Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching (CPC, NM), pp. 502–506.
DAC-1999-ChenW #approximate #bound #fault
Error Bounded Padé Approximation via Bilinear Conformal Transformation (CPC, DFW), pp. 7–12.
DAC-1997-ChenW
Optimal Wire-Sizing Function with Fringing Capacitance Consideration (CPC, DFW), pp. 604–607.
DAC-1996-ChenCW #optimisation #performance
Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation (CPC, YWC, DFW), pp. 405–408.
DAC-1996-ChenCW96a
Optimal Wire-Sizing Formular Under the Elmore Delay Model (CPC, YPC, DFW), pp. 487–490.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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