BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
15 × USA
2 × Germany
3 × France
Collaborated with:
C.Chen X.Tang M.Lai Y.Gao H.Zhou J.F.Croix K.Zhu T.Wang Y.Cai C.L.Liu I.Liu L.Huang R.Tian A.Aziz H.Xiang C.C.N.Chu W.Mak R.Rajaraman M.Guruswamy P.S.Sakhamuri J.Cong H.Chen R.Boone M.R.Korupolu K.K.Lee Y.Chang Y.Chen S.Thakur S.Krishnamoorthy G.G.Lai D.S.Fussell K.The J.Cong
Talks about:
optim (15) buffer (8) delay (8) rout (8) algorithm (7) minim (7) floorplan (6) insert (6) base (6) model (5)

Person: D. F. Wong


Contributed to:

DAC 20032003
DATE 20032003
DAC 20022002
DATE 20022002
DATE 20012001
DAC 20002000
DATE 20002000
DAC 19991999
DAC 19981998
DATE 19981998
DAC 19971997
DAC 19961996
DAC 19951995
DAC 19941994
DAC 19931993
DAC 19921992
DAC 19911991
DAC 19901990
DAC 19891989
DAC 19881988
DAC 19871987
DAC 19861986

Wrote 39 papers:

DAC-2003-CroixW #analysis #modelling #using
Blade and razor: cell and interconnect delay analysis using current-based models (JFC, DFW), pp. 386–389.
DATE-2003-HuangCW #nondeterminism
Global Wire Bus Configuration with Minimum Delay Uncertainty (LDH, HMC, DFW), pp. 10050–10055.
DAC-2002-TangW #constraints #performance
Floorplanning with alignment and performance constraints (XT, DFW), pp. 848–853.
DAC-2002-XiangWT #algorithm
An algorithm for integrated pin assignment and buffer planning (HX, DFW, XT), pp. 584–589.
DATE-2002-HuangLWG #constraints
Maze Routing with Buffer Insertion under Transition Time Constraints (LDH, ML, DFW, YG), pp. 702–707.
DATE-2002-HuangTXWL #algorithm #polynomial #problem
A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem (LDH, XT, HX, DFW, IML), pp. 470–475.
DATE-2001-GaoW #algorithm #graph #modelling
A graph based algorithm for optimal buffer insertion under accurate delay models (YG, DFW), pp. 535–539.
DATE-2001-LaiW #representation #slicing
Slicing tree is a complete floorplan representation (ML, DFW), pp. 228–232.
Maze routing with buffer insertion and wiresizing (ML, DFW), pp. 374–378.
DAC-2000-TianWB #modelling
Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability (RT, DFW, RB), pp. 667–670.
DAC-2000-ZhouW #composition #power management
Optimal low power X OR gate decomposition (HZ, DFW), pp. 104–107.
DATE-2000-GaoW #using
Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model (YG, DFW), pp. 512–516.
DATE-2000-LiuAW #constraints
Meeting Delay Constraints in DSM by Minimal Repeater Insertion (IML, AA, DFW), pp. 436–440.
DATE-2000-TangWT #evaluation #performance #sequence
Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation (XT, DFW, RT), pp. 106–111.
DAC-1999-ChenW #approximate #bound #fault
Error Bounded Padé Approximation via Bilinear Conformal Transformation (CPC, DFW), pp. 7–12.
DAC-1999-ZhouWLA #strict
Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations (HZ, DFW, IML, AA), pp. 96–99.
DAC-1998-KorupoluLW #independence #logic
Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs (MRK, KKL, DFW), pp. 708–711.
DAC-1998-ZhouW #constraints
Global Routing with Crosstalk Constraints (HZ, DFW), pp. 374–377.
DATE-1998-ChuW #algorithm #polynomial
A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing (CCNC, DFW), pp. 479–485.
Optimal Wire-Sizing Function with Fringing Capacitance Consideration (CPC, DFW), pp. 604–607.
DAC-1997-CroixW #logic #performance #synthesis
A Fast And Accurate Technique To Optimize Characterization Tables For Logic Synthesis (JFC, DFW), pp. 337–340.
DAC-1996-ChenCW #optimisation #performance
Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation (CPC, YWC, DFW), pp. 405–408.
Optimal Wire-Sizing Formular Under the Elmore Delay Model (CPC, YPC, DFW), pp. 487–490.
DAC-1996-ThakurWK #composition #multi
Delay Minimal Decomposition of Multiplexers in Technology Mapping (ST, DFW, SK), pp. 254–257.
DAC-1995-MakW #logic #on the
On Optimal Board-Level Routing for FPGA-Based Logic Emulation (WKM, DFW), pp. 552–556.
DAC-1994-ZhuW #bound
Switch Bound Allocation for Maximizing Routability in Timing-Driven Routing of FPGAs (KZ, DFW), pp. 165–170.
Clock Skew Minimization During FPGA Placement (KZ, DFW), pp. 232–237.
DAC-1993-LaiFW #data type #performance #query
HV/VH Trees: A New Spatial Data Structure for Fast Region Queries (GGL, DSF, DFW), pp. 43–47.
DAC-1993-RajaramanW #clustering
Optimal Clustering for Delay Minimization (RR, DFW), pp. 309–314.
DAC-1992-WangW #graph #optimisation
A Graph Theoretic Technique to Speed up Floorplan Area Optimization (TCW, DFW), pp. 62–68.
DAC-1991-CaiW #on the
On Minimizing the Number of L-Shaped Channels (YC, DFW), pp. 328–334.
DAC-1991-GuruswamyW #multi
A General Multi-Layer Area Router (MG, DFW), pp. 335–340.
DAC-1990-CaiW #algorithm #layout
A Channel/Switchbox Definition Algorithm for Building-Block Layout (YC, DFW), pp. 638–641.
DAC-1990-WangW #algorithm #optimisation
An Optimal Algorithm for Floorplan Area Optimization (TCW, DFW), pp. 180–186.
DAC-1989-TheWC #layout
VIA Minimization by Layout Modification (KST, DFW, JC), pp. 799–802.
DAC-1989-WongS #optimisation #performance
Efficient Floorplan Area Optimization (DFW, PSS), pp. 586–589.
DAC-1988-CongW #how
How to Obtain More Compactable Channel Routing Solutions (JC, DFW), pp. 663–666.
DAC-1987-WongL #array #optimisation #synthesis
Array Optimization for VLSI Synthesis (DFW, CLL), pp. 537–543.
DAC-1986-WongL #algorithm #design
A new algorithm for floorplan design (DFW, CLL), pp. 101–107.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.