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Travelled to:
2 × Germany
6 × USA
Collaborated with:
S.Abdi S.Zhao S.T.Healey A.Bilgory I.Viskic V.K.Raj B.M.Pangrle A.E.Casavant D.J.Kuck Y.Hwang G.Schirner F.Bacchini L.Maillet-Contoz H.Kashiwagi J.Donovan T.Mäkeläinen J.Greenbaum R.S.Nikhil
Talks about:
automat (3) silicon (2) generat (2) system (2) model (2) level (2) microprocessor (1) decomposit (1) heterogen (1) transact (1)

Person: Daniel D. Gajski

DBLP DBLP: Gajski:Daniel_D=

Contributed to:

DATE 20102010
DAC 20072007
LCTES 20072007
DATE 20052005
DAC 19851985
DAC 19841984
DAC 19811981
DAC 19801980

Wrote 10 papers:

DATE-2010-HwangSAG #modelling #transaction
Accurate timed RTOS model for transaction level modeling (YH, GS, SA, DDG), pp. 1333–1336.
DAC-2007-BacchiniGMKDMGN #named
TLM: Crossing Over From Buzz To Adoption (FB, DDG, LMC, HK, JD, TM, JG, RSN), pp. 444–445.
LCTES-2007-ViskicAG #automation #communication #embedded #generative #platform
Automatic generation of embedded communication SW for heterogeneous MPSoC platforms (IV, SA, DDG), pp. 143–145.
DATE-2005-AbdiG #functional #scheduling #validation
Functional Validation of System Level Static Scheduling (SA, DDG), pp. 542–547.
DATE-2005-ZhaoG #semantics
Defining an Enhanced RTL Semantics (SZ, DDG), pp. 548–553.
DAC-1985-HealeyG #composition #logic #network
Decomposition of logic networks into silicon (STH, DDG), pp. 162–168.
DAC-1984-Gajski #compilation
Silicon compilers and expert systems for VLSI (DDG), pp. 86–87.
DAC-1984-RajPG #synthesis
Microprocessor synthesis (VKR, BMP, DDG), pp. 676–678.
DAC-1981-BilgoryG #automation #generative
Automatic generation of cells for recurrence structures (AB, DDG), pp. 306–313.
DAC-1980-CasavantGK #automation #dependence #design #graph
Automatic design with dependence graphs (AEC, DDG, DJK), pp. 506–515.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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