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Travelled to:
1 × France
3 × Germany
3 × USA
Collaborated with:
D.Gajski D.D.Gajski Y.Hwang E.Saboori H.Cho I.Viskic D.Shin G.Schirner
Talks about:
level (5) system (4) model (4) transact (3) automat (3) heterogen (2) function (2) communic (2) generat (2) embed (2)

Person: Samar Abdi

DBLP DBLP: Abdi:Samar

Contributed to:

DATE 20132013
DATE 20102010
DATE 20082008
LCTES 20072007
DATE 20052005
DAC 20042004
DAC 20032003

Wrote 8 papers:

DATE-2013-SabooriA #embedded #hybrid #manycore #prototype
Hybrid prototyping of multicore embedded systems (ES, SA), pp. 1627–1630.
DATE-2010-HwangSAG #modelling #transaction
Accurate timed RTOS model for transaction level modeling (YH, GS, SA, DDG), pp. 1333–1336.
DATE-2008-HwangAG #approximate #estimation #performance #transaction
Cycle-approximate Retargetable Performance Estimation at the Transaction Level (YH, SA, DG), pp. 3–8.
LCTES-2007-ChoAG #interface #manycore #modelling #synthesis #transaction
Interface synthesis for heterogeneous multi-core systems from transaction level models (HC, SA, DG), pp. 140–142.
LCTES-2007-ViskicAG #automation #communication #embedded #generative #platform
Automatic generation of embedded communication SW for heterogeneous MPSoC platforms (IV, SA, DDG), pp. 143–145.
DATE-2005-AbdiG #functional #scheduling #validation
Functional Validation of System Level Static Scheduling (SA, DDG), pp. 542–547.
DAC-2004-AbdiG #architecture #automation #functional #generative #specification
Automatic generation of equivalent architecture model from functional specification (SA, DG), pp. 608–613.
DAC-2003-AbdiSG #automation #communication #design #refinement
Automatic communication refinement for system level design (SA, DS, DG), pp. 300–305.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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