Travelled to:1 × France
1 × Portugal
1 × USA
Collaborated with:Y.Paek R.Ayyagari G.Uh S.Pasricha I.Issenin N.Dutt S.Ko J.W.Yoon J.Lee J.Jung S.Park Y.Kim
Talks about:interconnect (1) reconfigur (1) preprocess (1) processor (1) irregular (1) increment (1) strategi (1) schedul (1) regular (1) pattern (1)
Person: Doosan Cho
DBLP: Cho:Doosan
Contributed to:
2011
2008
2007Wrote 3 papers:
- DATE-2011-YoonLJPKPC #configuration management #embedded #incremental #named
- I2CRF: Incremental interconnect customization for embedded reconfigurable fabrics (JWY, JL, JJ, SP, YK, YP, DC), pp. 1346–1351.
- LCTES-2008-ChoPIDPK #array #compilation #data access #layout #optimisation
- Compiler driven data layout optimization for regular/irregular array access patterns (DC, SP, II, ND, YP, SK), pp. 41–50.
- CC-2007-ChoAUP #effectiveness #multi #preprocessor #scheduling
- Preprocessing Strategy for Effective Modulo Scheduling on Multi-issue Digital Signal Processors (DC, RA, GRU, YP), pp. 16–31.