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Travelled to:
1 × France
1 × Germany
6 × USA
Collaborated with:
N.D.Dutt M.Ben-Romdhane N.A.Kapadia ∅ H.Homayoun M.A.Makhzan A.V.Veidenbaum B.K.Donohoo C.Ohlsen C.Anderson E.Bozorgzadeh D.Cho I.Issenin N.Dutt Y.Paek S.Ko
Talks about:
architectur (3) communic (3) energi (3) embed (3) processor (2) synthesi (2) perform (2) improv (2) explor (2) effici (2)

Person: Sudeep Pasricha

DBLP DBLP: Pasricha:Sudeep

Contributed to:

DATE 20152015
DAC 20122012
DAC 20092009
DAC 20082008
LCTES 20082008
DATE 20062006
DAC 20052005
DAC 20042004

Wrote 9 papers:

DATE-2015-KapadiaP #adaptation #named #parallel #scheduling
VARSHA: variation and reliability-aware application scheduling with adaptive parallelism in the dark-silicon era (NAK, SP), pp. 1060–1065.
DAC-2012-DonohooOPA #embedded #energy #mobile
Exploiting spatiotemporal and device contexts for energy-efficient mobile embedded systems (BKD, CO, SP, CA), pp. 1278–1283.
DAC-2009-Pasricha #3d
Exploring serial vertical interconnects for 3D ICs (SP), pp. 581–586.
DAC-2008-HomayounPMV #embedded #energy #performance #scalability
Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency (HH, SP, MAM, AVV), pp. 68–71.
LCTES-2008-ChoPIDPK #array #compilation #data access #layout #optimisation
Compiler driven data layout optimization for regular/irregular array access patterns (DC, SP, II, ND, YP, SK), pp. 41–50.
LCTES-2008-HomayounPMV #adaptation #embedded #energy #performance
Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors (HH, SP, MAM, AVV), pp. 71–78.
DATE-2006-PasrichaD #architecture #communication #memory management #named
COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC (SP, NDD), pp. 700–705.
DAC-2005-PasrichaDBB #architecture #automation #communication #synthesis
Floorplan-aware automated synthesis of bus-based communication architectures (SP, NDD, EB, MBR), pp. 565–570.
DAC-2004-PasrichaDB #approach #architecture #communication #modelling #performance #transaction
Extending the transaction level modeling approach for fast communication architecture exploration (SP, NDD, MBR), pp. 113–118.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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