Travelled to:1 × Italy
1 × United Kingdom
3 × USA
Collaborated with:M.M.Swift A.J.Tack A.Welc A.Adl-Tabatabai T.Shpeisman X.Tian R.Narayanaswamy S.Lu G.Graefe H.Kimura H.A.Kuno J.Tucek M.Lillibridge A.C.Veitch L.Yen J.Bobba M.R.Marty K.E.Moore M.D.Hill D.A.Wood
Talks about:memori (6) transact (4) implement (2) parallel (2) system (2) design (2) nest (2) lightweight (1) mnemosyn (1) persist (1)
Person: Haris Volos
DBLP: Volos:Haris
Contributed to:
2014
20122011
2009
2009
2007Wrote 6 papers:
- VLDB-2015-GraefeVKKTLV14 #big data #in memory #performance
- In-Memory Performance for Big Data (GG, HV, HK, HAK, JT, ML, ACV), pp. 37–48.
- ASPLOS-2012-VolosTSL #concurrent #debugging #memory management #transaction
- Applying transactional memory to concurrency bugs (HV, AJT, MMS, SL), pp. 211–222.
- ASPLOS-2011-VolosTS #lightweight #memory management #named #persistent
- Mnemosyne: lightweight persistent memory (HV, AJT, MMS), pp. 91–104.
- ECOOP-2009-VolosWASTN #design #implementation #memory management #named #parallel #transaction
- NePaLTM: Design and Implementation of Nested Parallelism for Transactional Memory Systems (HV, AW, ARAT, TS, XT, RN), pp. 123–147.
- PPoPP-2009-VolosWASTN #design #implementation #memory management #named #parallel #transaction
- NePalTM: design and implementation of nested parallelism for transactional memory systems (HV, AW, ARAT, TS, XT, RN), pp. 291–292.
- HPCA-2007-YenBMMVHSW #hardware #memory management #named #transaction
- LogTM-SE: Decoupling Hardware Transactional Memory from Caches (LY, JB, MRM, KEM, HV, MDH, MMS, DAW), pp. 261–272.