BibSLEIGH — Mark_D

Travelled to:

1 × Italy
1 × Turkey
1 × United Kingdom
23 × USA

Collaborated with:

D.A.Wood ∅ M.M.Swift J.R.Larus M.Talluri Swapnil Haria J.Bobba M.Xu R.Bodík S.S.Mukherjee I.Schoinas D.J.Sorin A.Ailamaki K.E.Moore S.K.Reinhardt M.M.K.Martin D.J.DeWitt B.M.Beckmann M.Plakal J.Power E.Schnarr T.M.Chilimbi Y.Y.A.Khalidi Lena E. Olson David A. Wood 0001 M.J.Moravan S.Che M.R.Marty D.R.Hower B.A.Hechtman M.Lupon D.Hower P.Dudnik L.Yen M.Skounakis A.Condon M.S.Orr A.Yilmazer J.D.Bingham A.J.Hu S.D.Sharma A.Rogers J.H.Saltz Sanketh Nalli Haris Volos 0001 K.Keeton B.R.Gaster Y.Tian H.Volos B.Liblit Y.Zhou L.Iftode J.P.Singh K.Li B.R.Toonen A.R.Alameldeen R.M.Dickson C.J.Mauer

Talks about:

memori (14) support (5) system (5) transact (4) perform (4) use (4) address (3) coher (3) cach (3) log (3)

Person: Mark D. Hill

DBLP: Hill:Mark_D=

Contributed to:

2015

2014

2011

2009

2008

2007

2006

2005

2002

2001

2000

1999

1998

1997

1995

1994

1992

2017

2018

2020

Wrote 35 papers:

ASPLOS-2015-OrrCYBHW #using: Synchronization Using Remote-Scope Promotion (MSO, SC, AY, BMB, MDH, DAW), pp. 73–86.
ASPLOS-2014-HowerHBGHRW #memory management #modelling: Heterogeneous-race-free memory models (DRH, BAH, BMB, BRG, MDH, SKR, DAW), pp. 427–440.
HPCA-2014-HechtmanCHTBHRW #approach #consistency #named: QuickRelease: A throughput-oriented approach to release consistency on GPUs (BAH, SC, DRH, YT, BMB, MDH, SKR, DAW), pp. 189–200.
HPCA-2014-PowerHW #gpu: Supporting x86-64 address translation for 100s of GPU lanes (JP, MDH, DAW), pp. 568–578.
PPoPP-2014-Hill #architecture: 21st century computer architecture (MDH), pp. 1–2.
HPCA-2011-BobbaLHW #memory management #performance: Safe and efficient supervised memory systems (JB, ML, MDH, DAW), pp. 369–380.
HPCA-2011-HowerDHW #named: Calvin: Deterministic or not? Free will to choose (DH, PD, MDH, DAW), pp. 333–334.
HPCA-2009-Hill: Opportunities beyond single-core microprocessors (MDH), pp. 143–144.
PPoPP-2009-Hill: Opportunities beyond single-core microprocessors (MDH), p. 97.
HPCA-2008-Hill #manycore: Amdahl’s Law in the multicore era (MDH), p. 187.
VLDB-2008-Hill #memory management #question #transaction: Is transactional memory an oxymoron? (MDH), p. 1.
HPCA-2007-YenBMMVHSW #hardware #memory management #named #transaction: LogTM-SE: Decoupling Hardware Transactional Memory from Caches (LY, JB, MRM, KEM, HV, MDH, MMS, DAW), pp. 261–272.
ASPLOS-2006-MoravanBMYHLSW #memory management #transaction: Supporting nested transactional memory in logTM (MJM, JB, KEM, LY, MDH, BL, MMS, DAW), pp. 359–370.
ASPLOS-2006-XuHB #memory management #reduction #transitive: A regulated transitive reduction (RTR) for longer memory race recording (MX, MDH, RB), pp. 49–60.
HPCA-2006-MooreBMHW #memory management #named #transaction: LogTM: log-based transactional memory (KEM, JB, MJM, MDH, DAW), pp. 254–265.
HPCA-2005-MartyBHHMW #multi #using: Improving Multiple-CMP Systems Using Token Coherence (MRM, JDB, MDH, AJH, MMKM, DAW), pp. 328–339.
PLDI-2005-XuBH #detection #source code: A serializability violation detector for shared-memory server programs (MX, RB, MDH), pp. 1–14.
HPCA-2002-MartinSHW #adaptation: Bandwidth Adaptive Snooping (MMKM, DJS, MDH, DAW), pp. 251–262.
PLDI-2001-SchnarrHL #compilation #named: Facile: A Language and Compiler for High-Performance Processor Simulators (ES, MDH, JRL), pp. 321–331.
VLDB-2001-AilamakiDHS #performance #weaving: Weaving Relations for Cache Performance (AA, DJD, MDH, MS), pp. 169–180.
ASPLOS-2000-MartinSAADMMPHW #approach: Timestamp snooping: an approach for extending SMPs (MMKM, DJS, AA, ARA, RMD, CJM, KEM, MP, MDH, DAW), pp. 25–36.
HPCA-1999-CondonHPS #memory management #modelling #using: Using Lamport Clocks to Reason about Relaxed Memory Models (AC, MDH, MP, DJS), pp. 270–278.
PLDI-1999-ChilimbiHL #layout: Cache-Conscious Structure Layout (TMC, MDH, JRL), pp. 1–12.
VLDB-1999-AilamakiDHW #question: DBMSs on a Modern Processor: Where Does Time Go? (AA, DJD, MDH, DAW), pp. 266–277.
HPCA-1998-MukherjeeH #data transfer #design #interface #network: The Impact of Data Transfer and Buffering Alternatives on Network Interface Design (SSM, MDH), pp. 207–218.
HPCA-1998-SchoinasH #interface #network: Address Translation Mechanisms In Network Interfaces (IS, MDH), pp. 219–230.
PPoPP-1997-ZhouISLTSHW #consistency #evaluation #performance: Relaxed Consistency and Coherence Granularity in DSM Systems: A Performance Evaluation (YZ, LI, JPS, KL, BRT, IS, MDH, DAW), pp. 193–205.
PPoPP-1995-MukherjeeSHLRS #performance: Efficient Support for Irregular Applications on Distributed-Memory Machines (SSM, SDS, MDH, JRL, AR, JHS), pp. 68–79.
SOSP-1995-TalluriHK: A New Page Table for 64-bit Address Spaces (MT, MDH, YYAK), pp. 184–200.
ASPLOS-1994-TalluriH #operating system #performance: Surpassing the TLB Performance of Superpages with Less Operating System Support (MT, MDH), pp. 171–182.
ASPLOS-1992-HillLRW #hardware #memory management #multi #scalability: Cooperative Shared Memory: Software and Hardware Support for Scalable Multiprocesors (MDH, JRL, SKR, DAW), pp. 262–273.
ASPLOS-2017-NalliHHSVK #analysis #memory management #persistent: An Analysis of Persistent Memory Use with WHISPER (SN, SH, MDH, MMS, HV0, KK), pp. 135–148.
ASPLOS-2017-OlsonHW #interactive: Crossing Guard: Mediating Host-Accelerator Coherence Interactions (LEO, MDH, DAW0), pp. 163–176.
ASPLOS-2018-HariaHS #memory management: Devirtualizing Memory in Heterogeneous Systems (SH, MDH, MMS), pp. 637–650.
ASPLOS-2020-HariaHS #memory management #named #order #persistent: MOD: Minimally Ordered Durable Datastructures for Persistent Memory (SH, MDH, MMS), pp. 775–788.