Travelled to:2 × France
4 × USA
Collaborated with:N.Ishiura T.Ishihara K.Hirose S.Yajima H.Tomiyama M.Sugihara H.Date A.Inoue B.Shackleford M.Yasuda E.Okushi H.Koizumi T.Sakai Y.Tsuchida Y.Ooi Y.Ono H.Kano S.Kimura
Talks about:design (5) system (3) reduct (3) processor (2) techniqu (2) languag (2) hardwar (2) semant (2) power (2) embed (2)
Person: Hiroto Yasuura
DBLP: Yasuura:Hiroto
Contributed to:
20001998
1997199019891982Wrote 8 papers:
- DATE-2000-HiroseY #reduction
- A Bus Delay Reduction Technique Considering Crosstalk (KH, HY), pp. 441–445.
- DATE-2000-IshiharaY #embedded #reduction
- A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors (TI, HY), pp. 617–623.
- DATE-2000-SugiharaYD #analysis #approach
- Analysis and Minimization of Test Time in a Combined BIST and External Test Approach (MS, HY, HD), pp. 134–140.
- DATE-1998-TomiyamaIIY #design #reduction #scheduling
- Instruction Scheduling for Power Reduction in Processor-Based System Design (HT, TI, AI, HY), pp. 855–860.
- DAC-1997-ShacklefordYOKTY #design #embedded #optimisation
- Memory-CPU Size Optimization for Embedded System Designs (BS, MY, EO, HK, HT, HY), pp. 246–251.
- DAC-1990-IshiuraYY #behaviour #design #hardware #named #semantics
- NES: The Behavioral Model for the Formal Semantics of a Hardware Design Language UDL/I (NI, HY, SY), pp. 8–13.
- DAC-1989-YasuuraI #design #hardware #semantics #standard
- Semantics of a Hardware Design Language for Japanese Standardization (HY, NI), pp. 836–839.
- DAC-1982-SakaiTYOOKKY #design #interactive #logic #simulation
- An Interactive Simulation System for structured logic design — ISS (TS, YT, HY, YO, YO, HK, SK, SY), pp. 747–754.