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Travelled to:
1 × Germany
3 × France
3 × USA
Collaborated with:
V.Bertacco T.M.Austin S.Lu A.DeOrio
Talks about:
design (3) hardwar (2) multi (2) test (2) core (2) subsystem (1) processor (1) framework (1) distribut (1) multicor (1)

Person: Ilya Wagner

DBLP DBLP: Wagner:Ilya

Contributed to:

DATE 20112011
DATE 20092009
HPCA 20092009
DATE 20082008
DATE 20072007
DAC 20062006
DAC 20052005

Wrote 7 papers:

DATE-2011-WagnerL #distributed #framework #hardware
Distributed hardware matcher framework for SoC survivability (IW, SLL), pp. 305–310.
DATE-2009-WagnerB #hardware #manycore #named
Caspar: Hardware patching for multicore processors (IW, VB), pp. 658–663.
HPCA-2009-DeOrioWB #design #manycore #memory management #named #validation
Dacota: Post-silicon validation of the memory subsystem in multi-core designs (AD, IW, VB), pp. 405–416.
DATE-2008-WagnerB #adaptation #design #manycore #named #verification
MCjammer: Adaptive Verification for Multi-core Designs (IW, VB), pp. 670–675.
DATE-2007-WagnerB #semantics #trust
Engineering trust with semantic guardians (IW, VB), pp. 743–748.
DAC-2006-WagnerBA #design #logic
Shielding against design flaws with field repairable control logic (IW, VB, TMA), pp. 344–347.
DAC-2005-WagnerBA #approach #automation #generative #monitoring #named #process #testing
StressTest: an automatic approach to test generation via activity monitors (IW, VB, TMA), pp. 783–788.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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