Travelled to:2 × France
4 × USA
Collaborated with:V.Bertacco D.Chatterjee D.Fick D.Blaauw D.Sylvester I.Wagner Q.Li M.Burgess K.Aisopos L.Peh J.Hu G.K.Chen
Talks about:silicon (3) network (2) design (2) simul (2) multi (2) level (2) post (2) high (2) gate (2) core (2)
Person: Andrew DeOrio
DBLP: DeOrio:Andrew
Contributed to:
2013
2011201020092009
2009Wrote 9 papers:
- DATE-2013-DeOrioLBB #debugging #detection #machine learning
- Machine learning-based anomaly detection for post-silicon bug diagnosis (AD, QL, MB, VB), pp. 491–496.
- DAC-2011-DeOrioABP #architecture #distributed #manycore #named
- DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips (AD, KA, VB, LSP), pp. 912–917.
- DAC-2010-DeOrioB #automation #design #network #social
- Electronic design automation for social networks (AD, VB), pp. 621–622.
- DAC-2009-ChatterjeeDB #simulation
- Event-driven gate-level simulation with GP-GPUs (DC, AD, VB), pp. 557–562.
- DAC-2009-DeOrioB
- Human computing for EDA (AD, VB), pp. 621–622.
- DAC-2009-FickDHBBS #named #network #reliability
- Vicis: a reliable network for unreliable silicon (DF, AD, JH, VB, DB, DS), pp. 812–817.
- DATE-2009-ChatterjeeDB #named #simulation
- GCS: High-performance gate-level simulation with GPGPUs (DC, AD, VB), pp. 1332–1337.
- DATE-2009-FickDCBSB #algorithm #fault tolerance
- A highly resilient routing algorithm for fault-tolerant NoCs (DF, AD, GKC, VB, DS, DB), pp. 21–26.
- HPCA-2009-DeOrioWB #design #manycore #memory management #named #validation
- Dacota: Post-silicon validation of the memory subsystem in multi-core designs (AD, IW, VB), pp. 405–416.