Travelled to:2 × USA
3 × Germany
4 × France
Collaborated with:G.Sassatelli P.Benoit P.Maurine V.Lomné M.Robert D.Puschini R.Elbaz P.Guillemin M.Bardouillet G.Perin B.Godard J.M.Daga A.Dehbaoui F.Clermidy S.Senni R.M.Brum A.Gamatié B.Mussard C.Jalier D.Lattard A.A.Jerraya S.Z.Ahmed J.Eydoux L.Rouge J.Cuelle R.Soares N.Calazans A.Martinez Y.Akgul S.Lesecq E.Beigné I.M.Panades T.Gil C.Diou G.Cambon J.Galy C.Anguille C.Buatois J.Rigaud
Talks about:processor (4) power (3) dynam (3) techniqu (2) encrypt (2) analysi (2) memori (2) enhanc (2) applic (2) evalu (2)
Person: Lionel Torres
DBLP: Torres:Lionel
Contributed to:
2015
20142012201020092007200620052002Wrote 12 papers:
- DATE-2015-SenniBTSGM
- Potential applications based on NVM emerging technologies (SS, RMB, LT, GS, AG, BM), pp. 1012–1017.
- DAC-2014-AkgulPLBPBT #power management
- Power management through DVFS and dynamic body biasing in FD-SOI circuits (YA, DP, SL, EB, IMP, PB, LT), p. 6.
- DATE-2012-PerinTBM #analysis #implementation
- Amplitude demodulation-based EM analysis of different RSA implementations (GP, LT, PB, PM), pp. 1167–1172.
- DATE-2010-JalierLJSBT #mobile
- Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem (CJ, DL, AAJ, GS, PB, LT), pp. 184–189.
- DATE-2010-LomneDMTR #analysis #difference #preprocessor #statistics
- Differential Power Analysis enhancement with statistical preprocessing (VL, AD, PM, LT, MR), pp. 1301–1304.
- DATE-2009-AhmedERCST #performance #pipes and filters #programmable #reduction
- Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor (SZA, JE, LR, JBC, GS, LT), pp. 184–189.
- DATE-2009-LomneMTRSC #evaluation #logic #robust
- Evaluation on FPGA of triple rail logic robustness against DPA and DEMA (VL, PM, LT, MR, RS, NC), pp. 634–639.
- DATE-2009-PuschiniCBST #distributed #energy #latency
- Dynamic and distributed frequency assignment for energy and latency constrained MP-SoC (DP, FC, PB, GS, LT), pp. 1564–1567.
- DATE-2007-GodardDTS #design #embedded #evaluation #reliability
- Evaluation of design for reliability techniques in embedded flash memories (BG, JMD, LT, GS), pp. 1593–1598.
- DAC-2006-ElbazTSGBM #encryption
- A parallelized way to provide data encryption and integrity checking on a processor-memory bus (RE, LT, GS, PG, MB, AM), pp. 506–509.
- DATE-2005-ElbazTSGABBR #bibliography #encryption #hardware
- Hardware Engines for Bus Encryption: A Survey of Existing Techniques (RE, LT, GS, PG, CA, MB, CB, JBR), pp. 40–45.
- DATE-2002-SassatelliTBGDCG #architecture #configuration management #scalability
- Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications (GS, LT, PB, TG, CD, GC, JG), pp. 553–558.