Travelled to:1 × China
1 × USA
Collaborated with:Y.Jiang M.Gu H.Zhang H.Zhang H.Liu D.Xiang S.Gu Y.Wu Y.Yang X.Zhao C.Sun X.Song
Talks about:model (3) test (3) scan (3) system (2) embed (2) cost (2) architectur (1) stateflow (1) heterogen (1) synthesi (1)
Person: Jia-Guang Sun
DBLP: Sun:Jia=Guang
Contributed to:
2014
2003
2016Wrote 4 papers:
- FSE-2014-JiangZZZLSSGS #embedded #modelling #multi #named #synthesis #tool support #validation
- Tsmart-GalsBlock: a toolkit for modeling, validation, and synthesis of multi-clocked embedded systems (YJ, HZ, HZ, XZ, HL, CS, XS, MG, JGS), pp. 711–714.
- DAC-2003-XiangGSW #architecture #effectiveness #testing
- A cost-effective scan architecture for scan testing with non-scan test power and test application cost (DX, SG, JGS, YLW), pp. 744–747.
- ASE-2016-YangJGS #approach #automaton #verification
- Verifying simulink stateflow model: timed automata approach (YY, YJ, MG, JGS), pp. 852–857.
- ASE-2016-ZhangJLZGS #design #embedded #modelling
- Model driven design of heterogeneous synchronous embedded systems (HZ, YJ, HL, HZ, MG, JGS), pp. 774–779.