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Travelled to:
1 × Canada
1 × China
1 × Germany
1 × Taiwan
2 × Russia
2 × USA
Collaborated with:
W.N.N.Hung G.Yang M.A.Perkowski J.Sun M.Gu O.Neiroukh Y.Jiang H.Zhang M.Z.0001 M.G.0001 Y.Xu E.Cerny F.Corella H.Liu F.Xie H.Kong F.He J.Yang O.A.Mohamed X.Cheng Y.Wang Y.J.0001 Z.Li Y.Deng H.Zhang X.Zhao C.Sun J.Sun K.D.Anon N.Boulerice M.Langevin S.Tahar Z.Zhou
Talks about:
synthesi (4) quantum (4) system (4) use (4) analysi (3) logic (3) gate (3) techniqu (2) reachabl (2) circuit (2)

Person: Xiaoyu Song

DBLP DBLP: Song:Xiaoyu

Contributed to:

FSE 20142014
CAV 20132013
ESEC/FSE 20132013
CIAA 20062006
DATE 20052005
DAC 20042004
CAV 19981998
CAV 19961996
ASE 20172017

Wrote 12 papers:

FSE-2014-JiangZZZLSSGS #embedded #modelling #multi #named #synthesis #tool support #validation
Tsmart-GalsBlock: a toolkit for modeling, validation, and synthesis of multi-clocked embedded systems (YJ, HZ, HZ, XZ, HL, CS, XS, MG, JGS), pp. 711–714.
CAV-2013-KongHSHG #generative #hybrid #safety #verification
Exponential-Condition-Based Barrier Certificate Generation for Safety Verification of Hybrid Systems (HK, FH, XS, WNNH, MG), pp. 242–257.
ESEC-FSE-2013-JiangLZDSGS #design #embedded #multi #optimisation #using
Design and optimization of multi-clocked embedded systems using formal technique (YJ, ZL, HZ, YD, XS, MG, JS), pp. 703–706.
ESEC-FSE-2013-JiangZLSHGS #analysis #reliability #runtime
System reliability calculation based on the run-time analysis of ladder program (YJ, HZ, HL, XS, WNNH, MG, JS), pp. 695–698.
CIAA-2006-YangXSP #hybrid #quantum #synthesis
Universality of Hybrid Quantum Gates and Synthesis Without Ancilla Qudits (GY, FX, XS, MAP), pp. 279–280.
DATE-2005-NeiroukhS #statistics #using
Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques (ON, XS), pp. 294–299.
DATE-2005-YangHSP #logic #multi #quantum #synthesis #using
Exact Synthesis of 3-Qubit Quantum Circuits from Non-Binary Quantum Gates Using Multiple-Valued Logic and Group Theory (GY, WNNH, XS, MAP), pp. 434–435.
DAC-2004-HungSYYP #analysis #logic #quantum #reachability #synthesis
Quantum logic synthesis by symbolic reachability analysis (WNNH, XS, GY, JY, MAP), pp. 838–841.
CAV-1998-XuCSCM #first-order #graph #logic #model checking #multi #using
Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs (YX, EC, XS, FC, OAM), pp. 219–231.
CAV-1996-AnonBCCLSTXZ #design #tool support #verification
MDG Tools for the Verification of RTL Designs (KDA, NB, EC, FC, ML, XS, ST, YX, ZZ), pp. 433–436.
ASE-2017-ChengZS0S #automation #fault #integer #named #type inference
IntPTI: automatic integer error repair with proper-type inference (XC, MZ0, XS, MG0, JS), pp. 996–1001.
ASE-2017-WangZJS0S #optimisation #reachability #static analysis
A static analysis tool with optimizations for reachability determination (YW, MZ0, YJ0, XS, MG0, JS), pp. 925–930.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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