Travelled to:1 × France
2 × USA
Collaborated with:S.W.Director S.Sirichotiyakul D.Blaauw C.Oh R.Levy V.Zolotov T.Edwards A.Dharchoudhury R.Panda
Talks about:design (2) threshold (1) simultan (1) conceptu (1) environ (1) circuit (1) voltag (1) select (1) integr (1) driver (1)
Person: Jingyan Zuo
DBLP: Zuo:Jingyan
Contributed to:
2001
20001999Wrote 3 papers:
- DAC-2001-SirichotiyakulBOLZZ #modelling #worst-case
- Driver Modeling and Alignment for Worst-Case Delay Noise (SS, DB, CO, RL, VZ, JZ), pp. 720–725.
- DATE-2000-ZuoD #concept #design
- An Integrated Design Environment for Early Stage Conceptual Design (JZ, SWD), p. 754.
- DAC-1999-SirichotiyakulEOZDPB #power management
- Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing (SS, TE, CO, JZ, AD, RP, DB), pp. 436–441.