Travelled to:2 × France
4 × USA
Collaborated with:V.Zolotov D.Blaauw R.Panda S.Sirichotiyakul M.R.Becer J.Zuo R.Levy R.B.Brashear N.Menezes L.T.Pillage M.R.Mercer A.Glebov S.Gavrilov I.Algor I.N.Hajj T.Edwards A.Dharchoudhury G.Braca A.Dasgupta A.Grinshpon B.Orshav
Talks about:circuit (4) nois (4) analysi (3) size (2) threshold (1) submicron (1) crosstalk (1) simultan (1) statist (1) predict (1)
Person: Chanhee Oh
DBLP: Oh:Chanhee
Contributed to:
2004
20032001200019991994Wrote 6 papers:
- DATE-v2-2004-GlebovGZOPB #analysis
- False-Noise Analysis for Domino Circuits (AG, SG, VZ, CO, RP, MRB), pp. 784–789.
- DAC-2003-BecerBAPOZH #reduction
- Post-route gate sizing for crosstalk noise reduction (MRB, DB, IA, RP, CO, VZ, INH), pp. 954–957.
- DAC-2001-SirichotiyakulBOLZZ #modelling #worst-case
- Driver Modeling and Alignment for Worst-Case Delay Noise (SS, DB, CO, RL, VZ, JZ), pp. 720–725.
- DAC-2000-LevyBBDGOOSZ #analysis #design #named
- ClariNet: a noise analysis tool for deep submicron design (RL, DB, GB, AD, AG, CO, BO, SS, VZ), pp. 233–238.
- DAC-1999-SirichotiyakulEOZDPB #power management
- Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing (SS, TE, CO, JZ, AD, RP, DB), pp. 436–441.
- EDAC-1994-BrashearMOPM #analysis #performance #predict #statistics #using
- Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis (RBB, NM, CO, LTP, MRM), pp. 332–337.