Travelled to:4 × USA
Collaborated with:D.Blaauw C.Oh S.B.K.Vrudhula J.Zuo R.Levy V.Zolotov T.Edwards A.Dharchoudhury R.Panda G.Braca A.Dasgupta A.Grinshpon B.Orshav
Talks about:nois (3) likelihood (1) threshold (1) submicron (1) simultan (1) circuit (1) capacit (1) analysi (1) voltag (1) select (1)
Person: Supamas Sirichotiyakul
DBLP: Sirichotiyakul:Supamas
Contributed to:
2002200120001999Wrote 4 papers:
- DAC-2002-VrudhulaBS #estimation
- Estimation of the likelihood of capacitive coupling noise (SBKV, DB, SS), pp. 653–658.
- DAC-2001-SirichotiyakulBOLZZ #modelling #worst-case
- Driver Modeling and Alignment for Worst-Case Delay Noise (SS, DB, CO, RL, VZ, JZ), pp. 720–725.
- DAC-2000-LevyBBDGOOSZ #analysis #design #named
- ClariNet: a noise analysis tool for deep submicron design (RL, DB, GB, AD, AG, CO, BO, SS, VZ), pp. 233–238.
- DAC-1999-SirichotiyakulEOZDPB #power management
- Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing (SS, TE, CO, JZ, AD, RP, DB), pp. 436–441.