Travelled to:2 × France
Collaborated with:A.Rueda J.M.Quintana J.L.Huertas I.A.Grout E.J.Peralías J.L.Huertas A.M.D.Richardson
Talks about:analog (2) placement (1) algorithm (1) simultan (1) approach (1) testabl (1) realist (1) predict (1) perform (1) circuit (1)
Person: Juan A. Prieto
DBLP: Prieto:Juan_A=
Contributed to:
19981997Wrote 2 papers:
- DATE-1998-PrietoRGPHR #approach #design #fault #layout #predict #testing
- An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits (JAP, AR, IAG, EJP, JLH, AMDR), pp. 905–909.
- EDTC-1997-PrietoRQH #algorithm #optimisation
- A performance-driven placement algorithm with simultaneous Place&Route optimization for analog ICs (JAP, AR, JMQ, JLH), pp. 389–394.