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Travelled to:
1 × China
1 × Denmark
1 × Finland
1 × Spain
1 × Sweden
3 × USA
4 × Germany
5 × France
Collaborated with:
G.Logothetis T.Kropf A.Morgenstern T.Schüle R.Kumar Y.Bai D.Baudisch M.Gesell J.Brandt S.K.Shukla E.Vecchié J.Talpin R.Reetz M.Huhn
Talks about:
synchron (6) program (4) verif (4) abstract (3) system (3) symbol (3) time (3) hardwar (2) control (2) circuit (2)

Person: Klaus Schneider

DBLP DBLP: Schneider:Klaus

Contributed to:

DATE 20142014
PDP 20142014
IFM 20132013
SEFM 20132013
DATE 20102010
LCTES 20102010
DATE 20092009
VMCAI 20082008
DAC 20042004
SEFM 20042004
DATE 20032003
DATE 20022002
DATE 20002000
DATE 19991999
DATE 19981998
EDAC-ETC-EUROASIC 19941994
CADE 19921992
CAV 19911991

Wrote 18 papers:

DATE-2014-BaiS #network
Isochronous networks by construction (YB, KS), pp. 1–6.
PDP-2014-BaudischBS #communication #message passing #source code
Reducing the Communication of Message-Passing Systems Synthesized from Synchronous Programs (DB, YB, KS), pp. 444–451.
IFM-2013-MorgensternGS #game studies #incremental #induction #using
Solving Games Using Incremental Induction (AM, MG, KS), pp. 177–191.
SEFM-2013-GesellMS #verification
Lifting Verification Results for Preemption Statements (MG, AM, KS), pp. 91–105.
DATE-2010-BaudischBS #independence #parallel #source code #thread
Multithreaded code from synchronous programs: Extracting independent threads for OpenMP (DB, JB, KS), pp. 949–952.
LCTES-2010-BrandtSS #concurrent #specification
Translating concurrent action oriented specifications to synchronous guarded actions (JB, KS, SKS), pp. 47–56.
DATE-2009-VecchieTS #compilation #execution #imperative
Separate compilation and execution of imperative synchronous modules (EV, JPT, KS), pp. 1580–1583.
VMCAI-2008-MorgensternS #automaton #ltl
From LTL to Symbolically Represented Deterministic Automata (AM, KS), pp. 279–293.
DAC-2004-SchueleS #abstraction #analysis #assembly #execution #source code
Abstraction of assembler programs for symbolic worst case execution time analysis (TS, KS), pp. 107–112.
SEFM-2004-SchuleS #comparison #infinity #model checking #verification
Global vs. Local Model Checking: A Comparison of Verification Techniques for Infinite State Systems (TS, KS), pp. 67–76.
DATE-2003-LogothetisS #analysis #source code
Exact High Level WCET Analysis of Synchronous Programs by Symbolic State Space Exploration (GL, KS), pp. 10196–10203.
DATE-2002-LogothetisS #generative #modelling #realtime
Extending Synchronous Languages for Generating Abstract Real-Time Models (GL, KS), pp. 795–802.
DATE-2000-LogothetisS #abstraction #realtime
Abstraction from Counters: An Application on Real-Time Systems (GL, KS), pp. 486–493.
DATE-1999-HuhnSKL #verification
Verifying Imprecisely Working Arithmetic Circuits (MH, KS, TK, GL), p. 65–?.
DATE-1998-ReetzSK #hardware #specification #verification
Formal Specification in VHDL for Hardware Verification (RR, KS, TK), pp. 257–263.
EDAC-1994-SchneiderKK #verification
Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path (KS, TK, RK), pp. 648–652.
CADE-1992-SchneiderKK #proving
The FAUST — Prover (KS, RK, TK), pp. 766–770.
CAV-1991-SchneiderKK #automation #hardware #proving
Automating Most Parts of Hardware Proofs in HOL (KS, RK, TK), pp. 365–375.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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