BibSLEIGH
BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
EDIT!
CC-BY
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
1 × France
1 × Germany
1 × USA
Collaborated with:
J.Carrabina
Talks about:
symbol (3) circuit (2) switch (2) simul (2) level (2) increment (1) equival (1) analysi (1) result (1) partit (1)

Person: Lluis Ribas

DBLP DBLP: Ribas:Lluis

Contributed to:

DATE 19991999
DATE 19981998
DAC 19951995

Wrote 3 papers:

DATE-1999-RibasC #clustering #modelling
Digital MOS Circuit Partitioning with Symbolic Modeling (LR, JC), pp. 503–508.
DATE-1998-RibasC #equivalence #incremental #on the #reuse #simulation #verification
On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits (LR, JC), pp. 624–629.
DAC-1995-Ribas-XirgoC #analysis #fault #simulation
Analysis of Switch-Level Faults by Symbolic Simulation (LR, JC), pp. 352–357.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.