BibSLEIGH
BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
CC-BY
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Used together with:
system (42)
level (40)
model (37)
network (35)
simul (31)

Stem switch$ (all stems)

264 papers:

CASECASE-2015-HallettWSV #agile
Rapid bicycle gear switching based on physiological cues (EH, RW, SS, RV), pp. 377–382.
CASECASE-2015-JiaZAX #analysis #performance
Performance analysis of Bernoulli serial production lines with switch-on/off machine control (ZJ, LZ, JA, GX), pp. 477–482.
DACDAC-2015-ThieleAE #analysis #scheduling
Improving formal timing analysis of switched ethernet by exploiting FIFO scheduling (DT, PA, RE), p. 6.
DATEDATE-2015-ChenEC #3d #hybrid
Enabling vertical wormhole switching in 3D NoC-bus hybrid systems (CC, ME, SDC), pp. 507–512.
DATEDATE-2015-MaHJ #manycore
A packet-switched interconnect for many-core systems with BE and RT service (RM, ZH, AJ), pp. 980–983.
DATEDATE-2015-MazloumiM #hybrid #memory management #multi
A hybrid packet/circuit-switched router to accelerate memory access in NoC-based chip multiprocessors (AM, MM), pp. 908–911.
DATEDATE-2015-ThangamuthuCCL #analysis #network
Analysis of ethernet-switch traffic shapers for in-vehicle networking applications (ST, NC, PJLC, JJL), pp. 55–60.
TACASTACAS-2015-Nguyen0TP #bound #c #contest #lazy evaluation #source code
Unbounded Lazy-CSeq: A Lazy Sequentialization Tool for C Programs with Unbounded Context Switches — (Competition Contribution) (TLN, BF, SLT, GP), pp. 461–463.
STOCSTOC-2015-Czumaj #network #permutation #random #using
Random Permutations using Switching Networks (AC), pp. 703–712.
CHICHI-2015-MariakakisGAPW #mobile #named #using
SwitchBack: Using Focus and Saccade Tracking to Guide Users’ Attention for Mobile Task Resumption (AM, MG, MTIA, SNP, JOW), pp. 2953–2962.
CHICHI-2015-TungCYWC #automation #interactive #named
FlickBoard: Enabling Trackpad Interaction with Automatic Mode Switching on a Capacitive-sensing Keyboard (YCT, TYC, NHY, CW, MYC), pp. 1847–1850.
SIGIRSIGIR-2015-ArkhipovaGKS #evaluation #predict
Search Engine Evaluation based on Search Engine Switching Prediction (OA, LG, IK, PS), pp. 723–726.
HPCAHPCA-2015-ChrysosMRBV #named #network
SCOC: High-radix switches made of bufferless clos networks (NC, CM, MR, CB, BV), pp. 402–414.
CASECASE-2014-Gao #hybrid #towards
Towards a converse Lyapunov stability theory of hybrid impulsive and switching systems (RG), pp. 425–429.
CASECASE-2014-OhnishiY #performance
Switching control of DC-DC converters with Electric Double-Layer Capacitor based on control performance index (YO, TY), pp. 188–193.
DACDAC-2014-AbeyratneJKBDDM
Quality-of-Service for a High-Radix Switch (NA, SJ, YK, DB, RGD, RD, TNM), p. 6.
DACDAC-2014-RaoJDBDM #named #performance
VIX: Virtual Input Crossbar for Efficient Switch Allocation (SR, SJ, RD, DB, RGD, TNM), p. 6.
DATEDATE-2014-YangMPOP #logic #using
Complementary resistive switch based stateful logic operations using material implication (YY, JM, DKP, MO, SP), pp. 1–4.
STOCSTOC-2014-DekelDKP
Bandits with switching costs: T2/3 regret (OD, JD, TK, YP), pp. 459–467.
FMFM-2014-DuggiralaWMVM #modelling #parallel #precedence #protocol
Temporal Precedence Checking for Switched Models and Its Application to a Parallel Landing Protocol (PSD, LW, SM, MV, CAM), pp. 215–229.
ICFPICFP-2014-Winograd-CortH #first-order #how
Settable and non-interfering signal functions for FRP: how a first-order switch is more than enough (DWC, PH), pp. 213–225.
CHICHI-2014-EnsFI #effectiveness #interface
The personal cockpit: a spatial interface for effective task switching on head-worn displays (BME, RF, PPI), pp. 3171–3180.
HCIHIMI-AS-2014-NarumiOKTH #abstraction #comprehension
Switching the Level of Abstraction in Digital Exhibitions to Provide an Understanding of Mechanisms (TN, HO, RK, TT, MH), pp. 567–576.
EDOCEDOC-2014-PourmirzaDG #collaboration #runtime
Switching Parties in a Collaboration at Run-Time (SP, RMD, PWPJG), pp. 136–141.
ICMLICML-c2-2014-BellemareVT
Skip Context Tree Switching (MGB, JV, ET), pp. 1458–1466.
RecSysRecSys-2014-BraunhoferCR #hybrid #recommendation
Switching hybrid for cold-starting context-aware recommender systems (MB, VC, FR), pp. 349–352.
SACSAC-2014-ParkKC #framework #kernel #memory management #online #using
Cooperative kernel: online memory test platform using inter-kernel context switch and memory isolation (HP, DK, JC), pp. 1517–1522.
CBSECBSE-2013-YinQCH #component
Mode switch handling for the ProCom component model (HY, HQ, JC, HH), pp. 13–22.
CASECASE-2013-MartinezA #design
Optimal switched-type control design for a class of nonlinear systems (JCM, VA), pp. 1069–1074.
CASECASE-2013-OFlahertyE #bound #learning #sequence
Learning to locomote: Action sequences and switching boundaries (RO, ME), pp. 7–12.
DACDAC-2013-JangPK #simulation
An event-driven simulation methodology for integrated switching power supplies in SystemVerilog (JEJ, MJP, JK), p. 7.
DATEDATE-2013-DimitrakopoulosGNK #multi
Switch folding: network-on-chip routers with time-multiplexed output ports (GD, NG, CN, EK), pp. 344–349.
DATEDATE-2013-GhiribaldiBN #architecture #effectiveness #manycore
A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems (AG, DB, SMN), pp. 332–337.
DATEDATE-2013-HuangMSBP #effectiveness #performance
A fast and Effective DFT for test and diagnosis of power switches in SoCs (XH, JM, RAS, SB, DKP), pp. 1089–1092.
DATEDATE-2013-SchneiderZGMC #analysis #composition
Compositional analysis of switched ethernet topologies (RS, LZ, DG, AM, SC), pp. 1099–1104.
DATEDATE-2013-WangYWZ #3d #configuration management #manycore #network
3D reconfigurable power switch network for demand-supply matching between multi-output power converters and many-core microprocessors (KW, HY, BW, CZ), pp. 1643–1648.
FoSSaCSFoSSaCS-2013-BonnetC #bound
Bounded Context-Switching and Reentrant Locking (RB, RC), pp. 65–80.
CHICHI-2013-JuhlinZSF #design
Fashionable shape switching: explorations in outfit-centric design (OJ, YZ, CS, YF), pp. 1353–1362.
CHICHI-2013-VoelkerWB #evaluation
An evaluation of state switching methods for indirect touch systems (SV, CW, JOB), pp. 745–754.
CHICHI-2013-WarrC #mobile #web
Swipe vs. scroll: web page switching on mobile browsers (AW, EHC), pp. 2171–2174.
CSCWCSCW-2013-ScissorsG #quote
“Back and forth, back and forth”: channel switching in romantic couple conflict (LES, DG), pp. 237–248.
HCIHIMI-D-2013-ChangSCH #design #interface #layout #on the #performance #topic
On the Reading Performance of Text Layout, Switch Position, Topic of Text, and Luminance Contrast for Chinese E-books Interface Design (WTC, LHS, ZC, KCH), pp. 567–575.
CIKMCIKM-2013-IdaNM #independence #online #topic
Domain-dependent/independent topic switching model for online reviews with numerical ratings (YI, TN, TM), pp. 229–238.
ICMLICML-c1-2013-WulsinFL #correlation #markov #parsing #process #using
Parsing epileptic events using a Markov switching process model for correlated time series (DW, EBF, BL), pp. 356–364.
ICMLICML-c3-2013-Chatzis #infinity
Infinite Markov-Switching Maximum Entropy Discrimination Machines (SC), pp. 729–737.
SIGIRSIGIR-2013-SavenkovLL #behaviour #detection
Search engine switching detection based on user personal preferences and behavior patterns (DS, DL, QL), pp. 33–42.
SPLCSPLC-2013-KatoKMOHH #case study #development #network
Case study of applying SPLE to development of network switch products (TK, MK, TM, HO, KH, TH), pp. 198–207.
ASPLOSASPLOS-2013-GoiriKLNB #data transformation #energy
Parasol and GreenSwitch: managing datacenters powered by renewable energy (IG, WAK, KL, TDN, RB), pp. 51–64.
CBSECBSE-2012-YinCH #component #multi #towards
Towards mode switch handling in component-based multi-mode systems (HY, JC, HH), pp. 183–188.
DACDAC-2012-SatpathyDDMSB #multi #quality #self
High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service (SS, RD, RGD, TNM, DS, DB), pp. 406–411.
DATEDATE-2012-0002EGB #performance #using
Area efficient asynchronous SDM routers using 2-stage Clos switches (WS, DAE, JDG, WJB), pp. 1495–1500.
DATEDATE-2012-DimitrakopoulosK #metaprogramming #multi #network
Dynamic-priority arbiter and multiplexer soft macros for on-chip networks switches (GD, EK), pp. 542–545.
DATEDATE-2012-LiuJL #constant #parallel
Parallel probing: Dynamic and constant time setup procedure in circuit switching NoC (SL, AJ, ZL), pp. 1289–1294.
DATEDATE-2012-LiuTWY #simulation
A GPU-accelerated envelope-following method for switching power converter simulation (XL, SXDT, HW, HY), pp. 1349–1354.
DATEDATE-2012-PatilJCLYPLCC #logic
Weighted area technique for electromechanically enabled logic computation with cantilever-based NEMS switches (SP, MWJ, CLC, DL, ZY, WEP, DJL, SAC, TC), pp. 727–732.
DATEDATE-2012-RoxEG #analysis #design #network #using
Using timing analysis for the design of future switched based Ethernet automotive networks (JR, RE, PG), pp. 57–62.
DATEDATE-2012-ZhangWLJC #design #symmetry
Asymmetry of MTJ switching and its implication to STT-RAM designs (YZ, XW, YL, AKJ, YC), pp. 1313–1318.
STOCSTOC-2012-ChanP #analysis #bound #fourier #network
Tight bounds for monotone switching networks via fourier analysis (SMC, AP), pp. 495–504.
CHICHI-2012-ZhuHL #comprehension #online #social
To switch or not to switch: understanding social influence in online choices (HZ, BAH, YL), pp. 2257–2266.
SEKESEKE-2012-DingM #analysis #fuzzy #modelling
Modeling and Analysis of Switched Fuzzy Systems (ZD, JM), pp. 135–138.
OOPSLAOOPSLA-2012-SolodkyyRS #c++ #performance
Open and efficient type switch for C++ (YS, GDR, BS), pp. 963–982.
CASECASE-2011-Gomez-GutierrezCRRG #linear
Sliding mode observer for Switched Linear Systems (DGG, SC, ART, JJRL, SDG), pp. 725–730.
CASECASE-2011-HejriG #hybrid #modelling
Hybrid modeling and control of switching DC-DC converters via MLD systems (MH, AG), pp. 714–719.
DATEDATE-2011-LukasiewyczCM #concept #network #scheduling
FlexRay switch scheduling — A networking concept for electric vehicles (ML, SC, PM), pp. 76–81.
DATEDATE-2011-LuPRR #energy #optimisation
Stage number optimization for switched capacitor power converters in micro-scale energy harvesting (CL, SPP, VR, KR), pp. 770–775.
DATEDATE-2011-PasettiCTSDSF
Characterization of an Intelligent Power Switch for LED driving with control of wiring parasitics effects (GP, NC, FT, RS, PD, SS, LF), pp. 1119–1120.
DATEDATE-2011-SchenkelaarsVG #network #scheduling
Optimal scheduling of switched FlexRay networks (TS, BV, KG), pp. 926–931.
DATEDATE-2011-WangNKWRLMB #configuration management #using
High-temperature (>500°C) reconfigurable computing using silicon carbide NEMS switches (XW, SN, ARK, FGW, SR, THL, MM, SB), pp. 1065–1070.
CSCWCSCW-2011-TanakaF #estimation
Study of user interruptibility estimation based on focused application switching (TT, KF), pp. 721–724.
HCIDUXU-v2-2011-FleuryPL #challenge #ubiquitous #usability
Evaluating Ubiquitous Media Usability Challenges: Content Transfer and Channel Switching Delays (AF, JSP, LBL), pp. 404–413.
HCIHIMI-v1-2011-LifOLHS #multimodal
Multimodal Threat Cueing in Simulated Combat Vehicle with Tactile Information Switching between Threat and Waypoint Indication (PL, PAO, BL, JH, JS), pp. 454–461.
HCIHIMI-v1-2011-TanakaYSN #comparison #using
Characteristics of Comfortable Sheet Switches on Control Panels of Electrical Appliances: Comparison Using Older and Younger Users (YT, YY, MS, MN), pp. 498–507.
CIKMCIKM-2011-MirzaCCHH #detection #process
Switch detector: an activity spotting system for desktop (HTM, LC, GC, IH, XH), pp. 2285–2288.
SIGIRSIGIR-2011-GuoWZAD #comprehension #predict #why
Why searchers switch: understanding and predicting engine switching rationales (QG, RWW, YZ, BA, STD), pp. 335–344.
CASECASE-2010-JohnsonM #optimisation #using
Local planning using switching time optimization (ERJ, TDM), pp. 828–834.
DATEDATE-2010-JunYC #library #multi #network #synthesis
Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network (MJ, SY, EYC), pp. 1390–1395.
DATEDATE-2010-KarnerASW #network #runtime #simulation #using
Holistic simulation of FlexRay networks by using run-time model switching (MK, EA, CS, RW), pp. 544–549.
DATEDATE-2010-Mirza-AghatabarBG #algorithm #pipes and filters
Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modules (MMA, MAB, SKG), pp. 1249–1254.
CHICHI-2010-KernMS #named #visual notation
Gazemarks: gaze-based visual placeholders to ease attention switching (DK, PM, AS), pp. 2093–2102.
CHICHI-2010-XuC
Push-and-pull switching: window switching based on window overlapping (QX, GC), pp. 1335–1338.
HPDCHPDC-2010-HermenierLM #clustering
Cluster-wide context switch of virtualized jobs (FH, AL, JMM), pp. 658–666.
DATEDATE-2009-ModarressiSA #hybrid #network
A hybrid packet-circuit switched on-chip network based on SDM (MM, HSA, MA), pp. 566–569.
ICALPICALP-v2-2009-GuhaM #metric #multi
Multi-armed Bandits with Metric Switching Costs (SG, KM), pp. 496–507.
FMFM-2009-DaylightS #case study #design #on the
On the Difficulties of Concurrent-System Design, Illustrated with a 2×2 Switch Case Study (EGD, SKS), pp. 273–288.
CHICHI-2009-SalvucciTB #concurrent #formal method #multi #performance #towards
Toward a unified theory of the multitasking continuum: from concurrent performance to task switching, interruption, and resumption (DDS, NT, JPB), pp. 1819–1828.
HCIDHM-2009-Furstenau #ambiguity
Computational Nonlinear Dynamics Model of Percept Switching with Ambiguous Stimuli (NF), pp. 227–236.
CIKMCIKM-2009-WhiteD #behaviour #predict
Characterizing and predicting search engine switching behavior (RWW, STD), pp. 87–96.
SACSAC-2009-RossTA #data type #online #predict
Online annotation and prediction for regime switching data streams (GJR, DKT, NMA), pp. 1501–1505.
VMCAIVMCAI-2009-TalyGT #constraints #logic #theorem proving #using
Synthesizing Switching Logic Using Constraint Solving (AT, SG, AT), pp. 305–319.
DATEDATE-2008-AmelifardHFP #logic #multi #stack
A Current Source Model for CMOS Logic Cells Considering Multiple Input Switching and Stack Effect (BA, SH, HF, MP), pp. 568–573.
ICGTICGT-2008-JelinkovaK #graph #on the
On Switching to H-Free Graphs (EJ, JK), pp. 379–395.
CHICHI-2008-FitzmauriceMKGK #agile #named
PieCursor: merging pointing and command selection for rapid in-place tool switching (GWF, JM, AK, MG, GK), pp. 1361–1370.
CHICHI-2008-HoffmannBW #scalability #visual notation
Evaluating visual cues for window switching on large screens (RH, PB, DSW), pp. 929–938.
PADLPADL-2008-GiorgidzeN
Switched-On Yampa (GG, HN), pp. 282–298.
HPCAHPCA-2008-KimGWB #analysis #performance #using
System level analysis of fast, per-core DVFS using on-chip switching regulators (WK, MSG, GYW, DMB), pp. 123–134.
CASECASE-2007-FukuiNSMMF #automation #safety
Requirement of three-position enabling switches for installing in enabling devices to achieve operational safety of robotics and automation applications (TF, MN, YS, IM, AM, TF), pp. 111–116.
DACDAC-2007-ChanZ #modelling
Modeling Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops (HHYC, ZZ), pp. 430–435.
DACDAC-2007-LuLJ #network
Layered Switching for Networks on Chip (ZL, ML, AJ), pp. 122–127.
DATEDATE-2007-HosseinabadyDN #testing #using
Using the inter- and intra-switch regularity in NoC switch testing (MH, AD, ZN), pp. 361–366.
HCIHCI-AS-2007-ZhangOD #automation #communication #evaluation #performance
Performance Evaluation for Automatic Protection Switching in a CDMA-TDD Wireless Communication System (LZ, HO, TD), pp. 1200–1209.
RERE-2007-SalifuYN #monitoring #problem #specification
Specifying Monitoring and Switching Problems in Context (MS, YY, BN), pp. 211–220.
SACSAC-2007-KarmakarG #adaptation #distributed #protocol
Adaptive broadcast by distributed protocol switching (SK, AG), pp. 588–589.
DACDAC-2006-AminKMKC #library #multi
A multi-port current source model for multiple-input switching effects in CMOS library cells (CSA, CVK, NM, KK, EC), pp. 247–252.
DACDAC-2006-ChangSC #design #evaluation #trade-off
Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs (KCC, JSS, TFC), pp. 143–148.
DACDAC-2006-ZhouP #agile #embedded #low cost #realtime
Rapid and low-cost context-switch through embedded processor customization for real-time and control applications (XZ, PP), pp. 352–357.
DATEDATE-2006-HosseinabadyBBN #concurrent #testing
A concurrent testing method for NoC switches (MH, AB, MNB, ZN), pp. 1171–1176.
DATEDATE-2006-PionteckAK #configuration management
A dynamically reconfigurable packet-switched network-on-chip (TP, CA, RK), pp. 136–137.
DATEDATE-2006-SridharanC #modelling #multi #using
Modeling multiple input switching of CMOS gates in DSM technology using HDMR (JS, TC), pp. 626–631.
DATEDATE-2006-SteinhammerGAK
A time-triggered ethernet (TTE) switch (KS, PG, AA, HK), pp. 794–799.
AdaSIGAda-2006-ShindiC #benchmark #metric #performance
Evaluate the performance changes of processor simulator benchmarks When context switches are incorporated (RSS, SC), pp. 9–14.
ICPRICPR-v4-2006-LinO #network #recognition #speech
Switching Auxiliary Chains for Speech Recognition based on Dynamic Bayesian Networks (HL, ZO), pp. 258–261.
ICPRICPR-v4-2006-PeursumVW #linear
Observation-Switching Linear Dynamic Systems for Tracking Humans Through Unexpected Partial Occlusions by Scene Objects (PP, SV, GAWW), pp. 929–934.
ICPRICPR-v4-2006-TokaiH #layout #multi #navigation
Attention Navigation by Keeping Screen Layout for Switching Multiple Views (ST, HH), pp. 766–769.
ICSEICSE-2006-ZhangGG #automation #fault
Locating faults through automated predicate switching (XZ, NG, RG), pp. 272–281.
HPCAHPCA-2006-ConstantinidesPBZBMAO #architecture #named
BulletProof: a defect-tolerant CMP switch architecture (KC, SP, JAB, BZ, VB, SAM, TMA, MO), pp. 5–16.
DATEDATE-2005-KumarLTW #multi #probability #process #statistics
A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input Switching (YSK, JL, CT, JMW), pp. 770–775.
DATEDATE-2005-MarkovM #encryption #hardware #logic
Uniformly-Switching Logic for Cryptographic Hardware (ILM, DM), pp. 432–433.
DATEDATE-2005-YangWVSX #approach #design
Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach (SY, WW, NV, DNS, YX), pp. 64–69.
CIAACIAA-2005-PodlovchenkoRZ #equivalence #on the #problem #source code
On the Equivalence Problem for Programs with Mode Switching (RIP, DMR, VAZ), pp. 351–352.
CHICHI-2005-LiHGL #analysis #user interface
Experimental analysis of mode switching techniques in pen-based user interfaces (YL, KH, ZG, JAL), pp. 461–470.
ICMLICML-2005-ToussaintV #learning #modelling
Learning discontinuities with products-of-sigmoids for switching between local models (MT, SV), pp. 904–911.
DACDAC-2004-AgarwalDB #multi #statistics
Statistical gate delay model considering multiple input switching (AA, FD, DB), pp. 658–663.
DACDAC-2004-LuJ #using #verification
Verifying a gigabit ethernet switch using SMV (YL, MJ), pp. 230–233.
DATEDATE-v2-2004-HuangTL #fault tolerance #programmable
Fault Tolerance of Programmable Switch Blocks (JH, MBT, FL), pp. 1358–1359.
DATEDATE-v2-2004-TirumurtiKSC #approach #modelling #power management
A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit (CT, SK, SSK, YSC), pp. 1078–1083.
ITiCSEITiCSE-WGR-2004-Mason #education
Teaching by analogy: the switch statement (JM), pp. 105–107.
STOCSTOC-2004-AzarR #network
The zero-one principle for switching networks (YA, YR), pp. 64–71.
ICGTICGT-2004-EhrenfeuchtHHR
Embedding in Switching Classes with Skew Gains (AE, JH, TH, GR), pp. 257–270.
CHICHI-2004-CzerwinskiHW
A diary study of task switching and interruptions (MC, EH, SW), pp. 175–182.
ICPRICPR-v2-2004-BandoSDI #performance #realtime #visual notation
Switching Particle Filters for Efficient Real-time Visual Tracking (TB, TS, KD, SI), pp. 720–723.
ICPRICPR-v4-2004-ZajdelCK #multi #online
Online Multicamera Tracking with a Switching State-Space Model (WZ, ATC, BJAK), pp. 339–343.
DACDAC-2003-EjlaliM
Switch-level emulation (ARE, SGM), pp. 644–649.
DACDAC-2003-ThudiB
Non-iterative switching window computation for delay-noise (BT, DB), pp. 390–395.
DACDAC-2003-VasudevanR #using
Computation of noise spectral density in switched capacitor circuits using the mixed-frequency-time technique (VV, MR), pp. 538–541.
DATEDATE-2003-AdriahantenainaCGMZ #named #scalability
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network (AA, HC, AG, LM, CAZ), pp. 20070–20073.
STOCSTOC-2003-AzarR #multi #network
Management of multi-queue switches in QoS networks (YA, YR), pp. 82–89.
SACSAC-2003-MinOF #performance #predict
Performance Prediction of Wormhole Switching in Hypercubes with Bursty Traffic Pattern (GM, MOK, JDF), pp. 985–989.
HPCAHPCA-2003-HaoH #network
Active I/O Switches in System Area Networks (MH, MH), pp. 365–376.
PPoPPPPoPP-2003-KarwandeYL #clustering #communication #named #prototype
CC-MPI: a compiled communication capable MPI prototype for ethernet switched clusters (AK, XY, DKL), p. 3.
PPoPPPPoPP-2003-KarwandeYL03a #clustering #communication #named #prototype
CC-MPI: a compiled communication capable MPI prototype for ethernet switched clusters (AK, XY, DKL), pp. 95–106.
ICSTSAT-2003-LiSB #effectiveness #performance #satisfiability #using
A Local Search SAT Solver Using an Effective Switching Strategy and an Efficient Unit Propagation (XYL, MFMS, FB), pp. 53–68.
DACDAC-2002-JollyPM #automation #equivalence
Automated equivalence checking of switch level circuits (SJ, ANP, TM), pp. 299–304.
DACDAC-2002-WhelihanS #memory management #network #optimisation
Memory optimization in single chip network switch fabrics (DW, HS), pp. 530–535.
DACDAC-2002-YeMB #analysis #network #power management
Analysis of power consumption on switch fabrics in network routers (TTY, GDM, LB), pp. 524–529.
DATEDATE-2002-DingM02a #modelling #using
Accurate Estimating Simultaneous Switching Noises by Using Application Specific Device Modeling (LD, PM), pp. 1038–1043.
DATEDATE-2002-HassibiH #automation #design
Automated Optimal Design of Switched-Capacitor Filters (AH, MdMH), p. 1111.
FASEFASE-2002-KumarH #slicing #source code
Better Slicing of Programs with Jumps and Switches (SK, SH), pp. 96–112.
ICGTICGT-2002-HageHW #graph
Euler Graphs, Triangle-Free Graphs and Bipartite Graphs in Switching Classes (JH, TH, EW), pp. 148–160.
ICPRICPR-v1-2002-JeongKSS #gesture #linear #recognition #using
Two-Hand Gesture Recognition using Coupled Switching Linear Model (MHJ, YK, NS, YS), pp. 9–12.
ICPRICPR-v3-2002-JeongKSS02a #gesture #linear #recognition #using
Two-Hand Gesture Recognition Using Coupled Switching Linear Model (MHJ, YK, NS, YS), pp. 529–532.
ICPRICPR-v3-2002-Klette02a #problem
Switche May Solve Adjacency Problems (RK), pp. 907–910.
SACSAC-2002-Al-DubaiOM #network #scalability #towards
Towards a scalable broadcast in wormhole-switched mesh networks (AYAD, MOK, LMM), pp. 840–844.
DACDAC-2001-BhanjaR #dependence #modelling #network #probability #process #using
Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks (SB, NR), pp. 209–214.
DACDAC-2001-Bondalapati #architecture #configuration management #using
Parallelizing DSP Nested Loops on Reconfigurable Architectures using Data Context Switching (KB), pp. 273–276.
DACDAC-2001-ChenGB
A New Gate Delay Model for Simultaneous Switching and Its Applications (LCC, SKG, MAB), pp. 289–294.
DACDAC-2001-DoboliV #constraints #design #synthesis
Integrated High-Level Synthesis and Power-Net Routing for Digital Design under Switching Noise Constraints (AD, RV), pp. 629–634.
DACDAC-2001-FanLWC #2d #design #on the
On Optimum Switch Box Designs for 2-D FPGAs (HF, JL, YLW, CCC), pp. 203–208.
DACDAC-2001-JacomeVP #architecture #clustering
Clustered VLIW Architectures with Predicated Switching (MFJ, GdV, SP), pp. 696–701.
STOCSTOC-2001-KesselmanLMPSS
Buffer overflow management in QoS switches (AK, ZL, YM, BPS, BS, MS), pp. 520–529.
ICMLICML-2001-SeldinBT #markov #memory management #segmentation #sequence
Unsupervised Sequence Segmentation by a Mixture of Switching Variable Memory Markov Sources (YS, GB, NT), pp. 513–520.
SACSAC-2001-AsciaCP #adaptation #fuzzy #performance
An adaptive fuzzy threshold scheme for high performance shared-memory switches (GA, VC, DP), pp. 456–461.
ASEASE-2000-BoseM #automation #coordination #generative #policy
Systematic Generation of Dependable Change Coordination Plans for Automated Switching of Coordination Policies (PKB, MGM), p. 325–?.
DACDAC-2000-KahngMS #analysis #on the
On switch factor based analysis of coupled RC interconnects (ABK, SM, ES), pp. 79–84.
DACDAC-2000-KrishnaswamyCT #fault #simulation
A switch level fault simulation environment (VK, JC, TT), pp. 780–785.
DATEDATE-2000-CotaRABCL #reuse
Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte (ÉFC, MR, FA, YB, LC, ML), pp. 226–230.
DATEDATE-2000-GuerrierG #architecture
A Generic Architecture for On-Chip Packet-Switched Interconnections (PG, AG), pp. 250–256.
ICPRICPR-v2-2000-MenardDC #ambiguity #analysis #distance #modelling #using
Switching Regression Models Using Ambiguity and Distance Rejects: Application to Ionogram Analysis (MM, PAD, VC), pp. 2688–2691.
ICPRICPR-v3-2000-TissainayagamS #automation #multi #visual notation
Visual Tracking of Multiple Objects with Automatic Motion Model Switching (PT, DS), pp. 7146–7158.
DATEDATE-1999-BuhlerPKB #approach #performance #process #simulation #using
Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach (MB, MP, KK, UGB), p. 459–?.
ICSMEICSM-1999-FukudaYY #experience #quality
Experience Paper: Quality Improvement in Switching-System Software (TF, TY, TY), pp. 353–358.
AdaEuropeAdaEurope-1999-Kamrad #ada
An Application (Layer 7) Routing Switch with Ada95 Software (JMKI), pp. 250–262.
AdaEuropeAdaEurope-1999-KamradS #ada #implementation #runtime
An Ada Runtime System Implementation of the Ravenscar Profile for High Speed Application-Layer Data Switch (JMKI, BAS), pp. 26–38.
SACSAC-1999-PittsC #simulation #visualisation
Peripherality Based Level of Detail Switching as a Visualization Enhancement of High-Risk Simulations (GP, DC), pp. 98–104.
HPCAHPCA-1999-IyerB #framework #latency #memory management #multi
Switch Cache: A Framework for Improving the Remote Memory Access Latency of CC-NUMA Multiprocessors (RRI, LNB), pp. 152–160.
HPCAHPCA-1999-PirvuBN #performance
The Impact of Link Arbitration on Switch Performance (MP, LNB, NN), pp. 228–235.
DATEDATE-1998-BisdounisKGN #modelling
Switching Response Modeling of the CMOS Inverter for Sub-micron Devices (LB, OGK, CEG, SN), pp. 729–735.
DATEDATE-1998-MirRVH #analysis #fault
Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems (SM, AR, DV, JLH), pp. 810–814.
DATEDATE-1998-OhP
Gated Clock Routing Minimizing the Switched Capacitance (JO, MP), pp. 692–697.
DATEDATE-1998-RibasC #equivalence #incremental #on the #reuse #simulation #verification
On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits (LR, JC), pp. 624–629.
FMFM-1998-FujitaRH #case study #experience #parallel #protocol #verification
Two Real Formal Verification Experiences: ATM Switch Chip and Parallel Cache Protocol (MF, SPR, AJH), pp. 281–295.
ICGTTAGT-1998-EhrenfeuchtHHR #complexity #graph
Complexity Issues in Switching of Graphs (AE, JH, TH, GR), pp. 59–70.
HPCAHPCA-1998-KatevenisSS
Credit-Flow-Controlled ATM for MP Interconnection: The ATLAS I Single-Chip ATM Switch (MK, DNS, ES), pp. 47–56.
ISSTAISSTA-1998-GodefroidHJ #analysis #model checking #monitoring #using
Model Checking Without a Model: An Analysis of the Heart-Beat Monitor of a Telephone Switch Using VeriSoft (PG, RSH, LJJ), pp. 124–133.
DACDAC-1997-MirROPH #automation #evaluation #fault #named #simulation
SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems (SM, AR, TO, EJP, JLH), pp. 281–286.
DATEEDTC-1997-IhsD #synthesis
Test synthesis for DC test of switched-capacitors circuits (HI, CD), p. 616.
DATEEDTC-1997-ManichF #process
Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model (SM, JF), pp. 597–602.
STOCSTOC-1997-OstrovskyR #algorithm
Universal O(Congestion + Dilation + log1+epsilonN) Local Control Packet Switching Algorithms (RO, YR), pp. 644–653.
HCIHCI-CC-1997-MamiyaHSK
A New Way to Overcome the Uneasy Operation of Touch-Sensitive Displays by Incorporating “Click” Mechanism CC Switch (MM, HH, YS, MK), pp. 619–622.
HPCAHPCA-1997-KesavanBP #multi #network
Multicast on Irregular Switch-Based Networks with Wormhole Routing (RK, KB, DKP), pp. 48–57.
HPDCHPDC-1997-Liebhart #aspect-oriented #performance
Performance Aspects of Switched SCI Systems (ML), pp. 223–231.
DACDAC-1996-LeeHCF #design #modelling #synthesis #using
Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL (MTCL, YCH, BC, MF), pp. 585–590.
DACDAC-1996-LimSPS #approach #estimation #process #statistics
A Statistical Approach to the Estimation of Delay Dependent Switching Activities in CMOS Combinational Circuits (YJL, KIS, HJP, MS), pp. 445–450.
STOCSTOC-1996-RabaniT #distributed #network
Distributed Packet Switching in Arbitrary Networks (YR, ÉT), pp. 366–375.
ICSEICSE-1996-Binder #development
A Telecommunication Development: Siemens’ Digital Switching System, EWSD (Abstract) (HEB), p. 587.
HPCAHPCA-1996-KarlssonS #clustering #evaluation #multi #performance
Performance Evaluation of a Cluster-Based Multiprocessor Built from ATM Switches and Bus-Based Multiprocessor Servers (MK, PS), pp. 4–13.
DACDAC-1995-NajmZ #process #worst-case
Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI Circuits (FNN, MYZ), pp. 623–627.
DACDAC-1995-Ribas-XirgoC #analysis #fault #simulation
Analysis of Switch-Level Faults by Symbolic Simulation (LR, JC), pp. 352–357.
DACDAC-1995-WempleY #analysis #megamodelling #using
Mixed-Signal Switching Noise Analysis Using Voronoi-Tessellated Substrate Macromodels (ILW, ATY), pp. 439–444.
HPCAHPCA-1995-CappelloG #communication #network #performance #towards
Toward High Communication Performance through Compiled Communications on a Circuit Switched Interconnection Network (FC, CG), pp. 44–53.
DACDAC-1994-DahlgrenL #modelling #network
Modeling of Intermediate Node States in switch-Level Networks (PD, PL), pp. 722–727.
DACDAC-1994-DrechslerSTBP #diagrams #functional #order #performance #representation
Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams (RD, AS, MT, BB, MAP), pp. 415–419.
DACDAC-1994-MonteiroDL #estimation #logic #performance #process
A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits (JCM, SD, BL), pp. 12–17.
DACDAC-1994-XakellisN #estimation #process #statistics
Statistical Estimation of the Switching Activity in Digital Circuits (MGX, FNN), pp. 728–733.
DACDAC-1994-ZhuW #bound
Switch Bound Allocation for Maximizing Routability in Timing-Driven Routing of FPGAs (KZ, DFW), pp. 165–170.
DATEEDAC-1994-AbderrahmanKS #estimation
Estimation of Simultaneous Switching Power and Ground Noise of Static CMOS Combinational Circuits (AA, BK, YS), p. 658.
DATEEDAC-1994-CalvoPM
ICM2 IC: a new ATM switching element for 2.48 Gb/s communications (FC, PP, PM), pp. 65–69.
DATEEDAC-1994-GevaertVNS
Switched Current Sigma-Delta A/D Converter for a CMOS Subscriber Line Analog Front End (DG, JV, JN, JS), pp. 75–79.
DACDAC-1993-MeyerC #fault #multi #performance #simulation
Fast Hierarchical Multi-Level Fault Simulation of Sequential Circuits with Switch-Level Accuracy (WM, RC), pp. 515–519.
FMFME-1993-LeonYSCG #design #experience #industrial #prototype
An Industrial Experience on LOTOS-Based Prototyping for Switching Systems Design (GL, JCY, CS, FJC, JJG), pp. 83–92.
HPDCHPDC-1993-ChenFFFRWY #distributed #interface #programming #prototype #scalability
A Low-Latency Programming Interface and a Prototype Switch for Scalable High-Performance Distributed Computing (TC, JF, GF, GF, SR, BW, FKY), pp. 160–168.
HPDCHPDC-1993-MaR #composition #multi #named #queue
MULTIPAR: An Output Queue ATM Modular Switch with Multiple Phases and Replicated Planes (JM, KR), pp. 152–159.
HPDCHPDC-1993-VarmaSB #evaluation #performance #standard
Performance Evaluation of a High-Speed Switching System Based on the Fibre Channel Standard (AV, VS, RB), pp. 144–151.
DACDAC-1992-GhoshDKW #estimation #process
Estimation of Average Switching Activity in Combinational and Sequential Circuits (AG, SD, KK, JW), pp. 253–259.
DACDAC-1992-Jones #incremental
Zero Delay versus Positive Delay in an Incremental Switch-Level Simulator (LGJ), pp. 424–427.
DACDAC-1992-LeeNB #generative #named #testing
SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits (KJL, CN, MAB), pp. 26–29.
ASPLOSASPLOS-1992-AndersonOST #network #scheduling
High Speed Switch Scheduling for Local Area Networks (TEA, SSO, JBS, CPT), pp. 98–110.
HPDCHPDC-1992-GuhaA #distributed #scalability
A Scalable Packet Switch for Distributed Computing (AG, MA), pp. 85–93.
DACDAC-1991-JainB #hardware #simulation
Mapping Switch-Level Simulation onto Gate-Level Hardware Accelerators (AJ, REB), pp. 219–222.
DACDAC-1991-Jones91a #simulation
Accelerating Switch-Level Simulation by Function Caching (LGJ), pp. 211–214.
DACDAC-1991-VandrisS #algorithm #fault #memory management #performance #simulation
Algorithms for Fast, Memory Efficient Switch-Level Fault Simulation (EV, GES), pp. 138–143.
FMVDME-1991-1-ZaveJ #specification
Techniques for Partial Specification and Specification of Switching Systems (PZ, MJ), pp. 511–525.
ASPLOSASPLOS-1991-MogulB #performance
The Effect of Context Switches on Cache Performance (JCM, AB), pp. 75–84.
SEKESEKE-1990-HsuehL #knowledge-based #programming
Knowledge-Based Programming for Call Processing Program in Telecommunication Switching System (JCCH, DTL), pp. 110–115.
DACDAC-1989-BlaauwSMAR #automation #behaviour #generative #modelling
Automatic Generation of Behavioral Models from Switch-Level Descriptions (DB, DGS, RBMT, JAA, JTR), pp. 179–184.
DACDAC-1989-KravitzBR #parallel #simulation
Massively Parallel Switch-Level Simulation: A Feasibility Study (SAK, REB, RAR), pp. 91–97.
DACDAC-1989-SalzH #incremental #named
IRSIM: An Incremental MOS Switch-Level Simulator (AS, MH), pp. 173–178.
SEKESEKE-1989-Anderson #design
Software Design for the 5ESS(R) Switch (LGA), p. 59.
SEKESEKE-1989-Meyers #performance #verification
Performance Verification of the AT&T 5ESSOR Switch (MNM), p. 60.
SEKESEKE-1989-Thanawala #specification
Requirement Specifications For The AT8T 5ESS(R) Switch (RCT), p. 58.
ICLPNACLP-1989-Mudambi #analysis #multi #performance
Performance Analysis of Aurora on a Switch-Based Multiprocessor (SM), pp. 697–712.
DACDAC-1988-Adler #logic #simulation
A Dynamically-Directed Switch Model for MOS Logic Simulation (DA), pp. 506–511.
DACDAC-1988-Cirit #analysis #random #testing
Switch Level Random Pattern Testability Analysis (MAC), pp. 587–590.
DACDAC-1988-KonczykowskaB #automation #design
Automated Design Software for Switched-Capacitor IC’s with Symbolic Simulator SCYMBAL (AK, MB), pp. 363–368.
ICSEICSE-1988-BarbacciWW #programming
Programming at the Processor-Memory-Switch Level (MB, CBW, JMW), pp. 19–29.
LICSLICS-1988-HoareG #correctness #logic
Partial Correctness of C-MOS Switching Circuits: An Exercise in Applied Logic (CARH, MJCG), pp. 28–36.
DACDAC-1987-McDermottS #network #paradigm
Switch Directed Dynamic Causal Networks — a Paradigm for Electronic System Diagnosis (RMM, DS), pp. 258–264.
DACDAC-1987-RajsumanMJ #fault #modelling #on the
On Accuracy of Switch-Level Modeling of Bridging Faults in Complex Gates (RR, YKM, APJ), pp. 244–250.
DACDAC-1987-Smith #hardware #scalability
A Hardware Switch Level Simulator for Large MOS Circuits (MTS), pp. 95–100.
DACDAC-1986-Adler #multi #named
SIMMOS: a multiple-delay switch-level simulator (DA), pp. 159–163.
DACDAC-1986-BarzilaiBHIS #analysis #fault #named #performance #verification
SLS — a fast switch level simulator for verification and fault coverage analysis (ZB, DKB, LMH, VSI, GMS), pp. 164–170.
DACDAC-1986-Frank #parallel #simulation
Exploiting parallelism in a switch-level simulation machine (EHF), pp. 20–26.
DACDAC-1986-HwangKN #modelling #verification
An accuration delay modeling technique for switch-level timing verification (SHH, YHK, ARN), pp. 227–233.
DACDAC-1985-AshokCS #data flow #modelling #simulation #using
Modeling switch-level simulation using data flow (VA, RLC, PS), pp. 637–644.
DACDAC-1985-BryantS #concurrent #evaluation #fault #performance
Performance evaluation of FMOSSIM, a concurrent switch-level fault simulator (REB, MDS), pp. 715–719.
DACDAC-1985-Frank #data-driven #simulation #using
Switch-level simulation of VLSI using a special-purpose data-driven computer (EHF), pp. 735–738.
DACDAC-1984-Ousterhout #modelling
Switch-level delay models for digital MOS VLSI (JKO), pp. 542–548.
DACDAC-1983-Ramachandran
An improved switch-level simulator for MOS circuits (VR), pp. 293–299.
DACDAC-1982-LightnerH #algorithm #functional #megamodelling #testing
Implication algorithms for MOS switch level functional macromodeling implication and testing (MRL, GDH), pp. 691–698.
DACDAC-1981-Bryant #named
MOSSIM: A switch-level simulator for MOS LSI (REB), pp. 786–790.
DACDAC-1981-HosakaUM #automation #design
A design automation system for electronic switching systems (TH, KU, HM), pp. 51–58.
SOSPSOSP-1981-LudererCHKM #distributed
A Distributed UNIX System Based on a Virtual Circuit Switch (GWRL, HC, JPH, PAK, WTM), pp. 160–168.
STOCSTOC-1980-Toueg #network
Deadlock- and Livelock-Free Packet Switching Networks (ST), pp. 94–99.
STOCSTOC-1979-TouegU #concurrent #network
Deadlock-Free Packet Switching Networks (ST, JDU), pp. 89–98.
FMFM-1979-Moriconi #design #interactive #network #verification
Interactive Design and Verification: A Message Switching Network Example (MM), pp. 355–388.
STOCSTOC-1978-Wegener #complexity #polynomial
Switching Functions Whose Monotone Complexity Is Nearly Quadratic (IW), pp. 143–149.
DACDAC-1977-Swiatek #automation #design
A design automation system for telephone electronic switching system (FES), pp. 419–424.
ICSEICSE-1976-ShankarC #abstraction #specification
Dat Flow, Abstraction Levels and Specifications for Communications Switching Systems (KSS, CSC), pp. 585–591.
DACDAC-1975-AlbertiniAJS #automation
Integrated automation program (I.A.P.) for an electronic switching system (FA, AA, PJ, AS), pp. 144–151.
DACDAC-1975-AllevaCGP #evaluation #implementation #simulation #source code
A simulation system for implementation and evaluation of diagnostic programs of a special-purpose telecommunication switching processor (IA, MGC, RG, FP), pp. 123–133.
DACDAC-1974-Kjelkerud #generative #performance #source code #testing
A system of computer programs for efficient test generation for combinational switching circuits (EK), pp. 166–168.
DACDAC-1973-HiranoH #design #logic
Computer aided design system for logic equipment applied to design of electronic switching equipment (TH, KH), pp. 205–212.
DACDAC-1972-ChangDE #analysis #fault #logic #self #simulation
Logic simulation and fault analysis of a self-checking switching processor (HYC, RCD, RAE), pp. 128–137.
DACDAC-1972-Schmidt #composition #network
Gate for gate modular replacement of combinational switching networks (DCS), pp. 331–340.
DACDAC-1970-Goetz #design
Computer aided diagnostic design for electronic switching systems (FMG), pp. 178–189.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.