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Travelled to:
1 × France
1 × Germany
1 × USA
Collaborated with:
L.Ribas J.Joven O.Font-Bach D.Castells-Rufas R.Martínez L.Terés
Talks about:
symbol (3) circuit (2) switch (2) simul (2) level (2) architectur (1) experiment (1) increment (1) distribut (1) parallel (1)

Person: Jordi Carrabina

DBLP DBLP: Carrabina:Jordi

Contributed to:

PDP 20082008
DATE 19991999
DATE 19981998
DAC 19951995

Wrote 4 papers:

PDP-2008-JovenFCMTC #architecture #distributed #named #parallel
xENoC — An eXperimental Network-On-Chip Environment for Parallel Distributed Computing on NoC-based MPSoC Architectures (JJ, OFB, DCR, RM, LT, JC), pp. 141–148.
DATE-1999-RibasC #clustering #modelling
Digital MOS Circuit Partitioning with Symbolic Modeling (LR, JC), pp. 503–508.
DATE-1998-RibasC #equivalence #incremental #on the #reuse #simulation #verification
On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits (LR, JC), pp. 624–629.
DAC-1995-Ribas-XirgoC #analysis #fault #simulation
Analysis of Switch-Level Faults by Symbolic Simulation (LR, JC), pp. 352–357.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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