Travelled to:2 × France
Collaborated with:C.G.Requena P.López J.Sahuquillo V.Selfa J.Duato D.Ludovici D.Bertozzi R.Peñaranda J.J.Valls A.Ros P.Navarro D.B.Garzón A.Strano M.Favalli F.G.Villamón S.Medardoni G.N.Gaydadjiev
Talks about:network (3) exploit (3) multiprogram (2) workload (2) topolog (2) perform (2) effici (2) design (2) chip (2) interconnect (1)
Person: María Engracia Gómez
DBLP: G=oacute=mez:Mar=iacute=a_Engracia
Contributed to:
20152014
201120092008Wrote 8 papers:
- PDP-2015-NavarroSSGR #design #locality #multi
- Row Tables: Design Choices to Exploit Bank Locality in Multiprogram Workloads (PN, VS, JS, MEG, CGR), pp. 22–26.
- PDP-2015-PenarandaRGL #adaptation #algorithm #named
- XORAdap: A HoL-Blocking Aware Adaptive Routing Algorithm (RP, CGR, MEG, PL), pp. 48–52.
- PDP-2015-SelfaSRG #metric #multi #performance
- Methodologies and Performance Metrics to Evaluate Multiprogram Workloads (VS, JS, CGR, MEG), pp. 150–154.
- PDP-2015-VallsSRG #approach #energy
- The Tag Filter Cache: An Energy-Efficient Approach (JJV, JS, AR, MEG), pp. 182–189.
- PDP-2014-GarzonGGLD #fault tolerance #named #performance
- FT-RUFT: A Performance and Fault-Tolerant Efficient Indirect Topology (DBG, CGR, MEG, PL, JD), pp. 405–409.
- DATE-2011-StranoGLFGB #architecture #scalability #self
- Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture (AS, CGR, DL, MF, MEG, DB), pp. 661–666.
- DATE-2009-LudoviciVMRGLGB #constraints #design
- Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints (DL, FGV, SM, CGR, MEG, PL, GNG, DB), pp. 562–565.
- PDP-2008-RequenaGLD #network
- Exploiting Wiring Resources on Interconnection Network: Increasing Path Diversity (CGR, MEG, PL, JD), pp. 20–29.