Travelled to:1 × Germany
2 × France
Collaborated with:D.Bertozzi M.Lajolo M.Ruggiero L.Benini G.Strano C.Pistritto D.Ludovici F.G.Villamón C.G.Requena M.E.Gómez P.López G.N.Gaydadjiev
Talks about:interact (2) memori (2) design (2) constraint (1) technolog (1) subsystem (1) platform (1) nanoscal (1) industri (1) communic (1)
Person: Simone Medardoni
DBLP: Medardoni:Simone
Contributed to:
200920082007Wrote 3 papers:
- DATE-2009-LudoviciVMRGLGB #constraints #design
- Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints (DL, FGV, SM, CGR, MEG, PL, GNG, DB), pp. 562–565.
- DATE-2008-MedardoniLB #design #self
- Variation tolerant NoC design by means of self-calibrating links (SM, ML, DB), pp. 1402–1407.
- DATE-2007-MedardoniRBBSP #communication #in memory #industrial #interactive #memory management #platform
- Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms (SM, MR, DB, LB, GS, CP), pp. 660–665.