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Travelled to:
2 × Germany
7 × France
Collaborated with:
C.Metra B.Riccò M.Dalpasso L.Schiano A.Bogliolo L.Benini P.Olivo A.Strano C.G.Requena D.Ludovici M.E.Gómez D.Bertozzi
Talks about:
test (5) self (4) detect (3) design (3) fault (3) check (3) line (3) scheme (2) error (2) code (2)

Person: Michele Favalli

DBLP DBLP: Favalli:Michele

Contributed to:

DATE 20112011
DATE 20072007
DATE 20022002
DATE 20012001
DATE 20002000
DATE 19991999
DATE 19981998
ED&TC 19971997
EDAC-ETC-EUROASIC 19941994

Wrote 12 papers:

DATE-2011-StranoGLFGB #architecture #scalability #self
Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture (AS, CGR, DL, MF, MEG, DB), pp. 661–666.
DATE-2007-FavalliM #detection #fault #interactive
Interactive presentation: Pulse propagation for the detection of small delay defects (MF, CM), pp. 1295–1300.
DATE-2002-FavalliD #approach #design #generative #pseudo #random testing
An Evolutionary Approach to the Design of On-Chip Pseudorandom Test Pattern Generators (MF, MD), p. 1122.
DATE-2002-FavalliM #fault #problem #self
Problems Due to Open Faults in the Interconnections of Self-Checking Data-Paths (MF, CM), pp. 612–617.
DATE-2002-MetraSRF #online #power management #self #testing
Self-Checking Scheme for the On-Line Testing of Power Supply Noise (CM, LS, BR, MF), pp. 832–836.
DATE-2001-FavalliM #detection #fault #optimisation
Optimization of error detecting codes for the detection of crosstalk originated errors (MF, CM), pp. 290–296.
DATE-2000-DalpassoBBF #design #distributed #fault #simulation
Virtual Fault Simulation of Distributed IP-Based Designs (MD, AB, LB, MF), pp. 99–103.
DATE-2000-MetraFR #online #testing
On-Line Testing and Diagnosis of Bus Lines with respect to Intermediate Voltage Values (CM, MF, BR), p. 763.
DATE-1999-FavalliM #design #functional #on the #self
On the Design of Self-Checking Functional Units Based on Shannon Circuits (MF, CM), pp. 368–375.
DATE-1998-MetraFR
Highly Testable and Compact 1-out-of-n Code Checker with Single Output (CM, MF, BR), pp. 981–982.
EDTC-1997-FavalliM #testing
Testing scheme for IC’s clocks (MF, CM), pp. 445–449.
EDAC-1994-FavalliDOR #fault #modelling
Modeling of Broken Connections Faults in CMOS ICs (MF, MD, PO, BR), pp. 159–164.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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