Travelled to:1 × Germany
2 × France
5 × USA
Collaborated with:D.Stoffel W.Kunz M.D.Nguyen G.Greuel J.Urdahl O.Wienand M.Thalmaier J.Bormann E.Pavlenko A.Dreyer F.Seelisch
Talks about:properti (3) arithmet (3) verif (3) check (3) base (3) abstract (2) algebra (2) reason (2) induct (2) comput (2)
Person: Markus Wedler
DBLP: Wedler:Markus
Contributed to:
20122011
20112010
2008200520042003Wrote 8 papers:
- DAC-2012-UrdahlSWK #abstraction #composition #concurrent #verification
- System verification of concurrent RTL modules by compositional path predicate abstraction (JU, DS, MW, WK), pp. 334–343.
- DAC-2011-NguyenWSK #abstraction #hardware
- Formal hardware/software co-verification by interval property checking with abstraction (MDN, MW, DS, WK), pp. 510–515.
- DATE-2011-PavlenkoWSKDSG #algebra #named #problem #reasoning #smt #verification
- STABLE: A new QF-BV SMT solver for hard verification problems combining Boolean reasoning with computer algebra (EP, MW, DS, WK, AD, FS, GMG), pp. 155–160.
- DAC-2010-ThalmaierNWSBK #induction #invariant #satisfiability
- Analyzing k-step induction to compute invariants for SAT-based property checking (MT, MDN, MW, DS, JB, WK), pp. 176–181.
- CAV-2008-WienandWSKG #algebra #approach #correctness #proving
- An Algebraic Approach for Proving Data Correctness in Arithmetic Data Paths (OW, MW, DS, WK, GMG), pp. 473–486.
- DAC-2005-WedlerSK #normalisation
- Normalization at the arithmetic bit level (MW, DS, WK), pp. 457–462.
- DATE-v1-2004-WedlerSK #reasoning #satisfiability
- Arithmetic Reasoning in DPLL-Based SAT Solving (MW, DS, WK), pp. 30–35.
- DATE-2003-WedlerSK #encoding #induction #using
- Using RTL Statespace Information and State Encoding for Induction Based Property Checking (MW, DS, WK), pp. 11156–11157.