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Travelled to:
1 × USA
Collaborated with:

Talks about:
transistor (1) testabl (1) pattern (1) circuit (1) analysi (1) switch (1) random (1) level (1) size (1) cmos (1)

Person: Mehmet A. Cirit

DBLP DBLP: Cirit:Mehmet_A=

Contributed to:

DAC 19881988
DAC 19871987

Wrote 2 papers:

DAC-1988-Cirit #analysis #random #testing
Switch Level Random Pattern Testability Analysis (MAC), pp. 587–590.
DAC-1987-Cirit
Transistor Sizing in CMOS Circuits (MAC), pp. 121–124.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.