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Travelled to:
1 × France
2 × Germany
Collaborated with:
S.Koranne S.G.Pestana A.Radulescu E.Rijpkema K.G.W.Goossens K.Goossens J.Dielissen
Talks about:
perform (2) network (2) design (2) chip (2) guarante (1) approach (1) geometr (1) automat (1) analysi (1) acceler (1)

Person: Om Prakash Gangwal

DBLP DBLP: Gangwal:Om_Prakash

Contributed to:

DATE 20052005
DATE v2 20042004
DATE 20012001

Wrote 3 papers:

DATE-2005-GoossensDGPRR #design #network #performance #verification
A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification (KG, JD, OPG, SGP, AR, ER), pp. 1182–1187.
DATE-v2-2004-PestanaRRGG #approach #network #trade-off
Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach (SGP, ER, AR, KGWG, OPG), pp. 764–769.
DATE-2001-KoranneG #analysis #automation #geometry #layout #on the
On automatic analysis of geometrically proximate nets in VSLI layout (SK, OPG), p. 818.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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