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Travelled to:
2 × USA
Collaborated with:
M.Kishinevsky D.Kadjo R.Ayoub J.Kim Elvira Teran D.A.Jiménez S.H.Pugsley C.Wilkerson X.Chen Z.Xu H.Kim J.Hu Ü.Y.Ogras R.Z.Ayoub
Talks about:
processor (2) program (2) reconstruct (1) subsystem (1) hierarchi (1) platform (1) multicor (1) frequenc (1) behavior (1) approach (1)

Person: Paul V. Gratz

DBLP DBLP: Gratz:Paul_V=

Contributed to:

DAC 20152015
DAC 20132013
ASPLOS 20172017

Wrote 3 papers:

DAC-2015-KadjoAKG #approach #cpu #energy #gpu #mobile #performance #platform
A control-theoretic approach for energy efficient CPU-GPU subsystem in mobile platforms (DK, RA, MK, PVG), p. 6.
DAC-2013-ChenXKGHKOA #design #manycore #scalability
Dynamic voltage and frequency scaling for shared resources in multicore processor designs (XC, ZX, HK, PVG, JH, MK, ÜYO, RZA), p. 7.
ASPLOS-2017-KimTGJPW #behaviour
Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy (JK, ET, PVG, DAJ, SHP, CW), pp. 737–749.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.