1 × Canada
1 × France
13 × USA
2 × Germany
S.S.Sapatnekar C.J.Alpert C.C.N.Sze S.Hu Y.Liu M.Kim C.Nass Y.Cai Q.Zhou W.Shi M.Ketkar K.Cao S.Dobre A.Rajaram R.N.Mahapatra X.Chen Z.Li C.Li W.Luo F.Yang Q.Li P.Li G.Venkataraman F.Liu M.Hrkic S.T.Quay H.Su S.R.Nassif P.Villarrubia R.Kumar B.Li Y.Shen U.Schlichtmann J.Won P.Gratz V.Soteriou A.Winterboer J.D.Moore R.Illowsky J.Pearson H.P.Branigan M.J.Pickering T.Jindal G.Nam C.B.Winn M.Brzozowski K.Carattini S.R.Klemmer P.Mihelich A.Y.Ng S.K.Karandikar Y.Lu X.Hong L.Huang Z.Xu H.Kim P.V.Gratz M.Kishinevsky Ü.Y.Ogras R.Z.Ayoub
base (5) network (4) buffer (4) clock (4) optim (3) skew (3) fast (3) placement (2) difficult (2) resourc (2)
Person: Jiang Hu
Wrote 23 papers:
- DAC-2015-LiLSH #approximate #optimisation #precise #synthesis
- Joint precision optimization and high level synthesis for approximate computing (CL, WL, SSS, JH), p. 6.
- DATE-2015-KumarLSSH #adaptation #verification
- Timing verification for adaptive integrated circuits (RK, BL, YS, US, JH), pp. 1587–1590.
- HPCA-2014-WonCGHS #learning #network #online #power management
- Up by their bootstraps: Online learning in Artificial Neural Networks for CMP uncore power management (JYW, XC, PG, JH, VS), pp. 308–319.
- DAC-2013-ChenXKGHKOA #design #manycore #scalability
- Dynamic voltage and frequency scaling for shared resources in multicore processor designs (XC, ZX, HK, PVG, JH, MK, ÜYO, RZA), p. 7.
- DAC-2010-JindalAHLNW #detection #logic
- Detecting tangled logic structures in VLSI netlists (TJ, CJA, JH, ZL, GJN, CBW), pp. 603–608.
- DATE-2010-YangCZH #multi #satisfiability
- SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal (FY, YC, QZ, JH), pp. 1369–1372.
- DAC-2009-LiuH #optimisation #parallel #performance
- GPU-based parallelization for fast circuit optimization (YL, JH), pp. 943–946.
- CHI-2007-HuWNMI #testing #usability
- Context & usability testing: user-modeled information presentation in easy and difficult driving conditions (JH, AW, CN, JDM, RI), pp. 1343–1346.
- DAC-2007-HuKH #design
- Gate Sizing For Cell Library-Based Designs (SH, MK, JH), pp. 847–852.
- CHI-2006-BrzozowskiCKMHN #named #scheduling
- groupTime: preference based group scheduling (MB, KC, SRK, PM, JH, AYN), pp. 1047–1056.
- CHI-2006-PearsonHBPN #adaptation #behaviour #how #human-computer #word
- Adaptive language behavior in HCI: how expectations and beliefs about a system affect users’ word choice (JP, JH, HPB, MJP, CN), pp. 1177–1180.
- DAC-2006-CaoDH #standard
- Standard cell characterization considering lithography induced variations (KC, SD, JH), pp. 801–804.
- DAC-2006-HuAHKLSS #algorithm #performance
- Fast algorithms for slew constrained minimum cost buffering (SH, CJA, JH, SKK, ZL, WS, CCNS), pp. 308–313.
- DAC-2006-HuLHL #network
- Steiner network construction for timing critical nets (SH, QL, JH, PL), pp. 379–384.
- Associative skew clock routing for difficult instances (MSK, JH), pp. 762–767.
- DATE-2006-VenkataramanHLS #optimisation
- Integrated placement and skew optimization for rotary clocking (GV, JH, FL, CCNS), pp. 756–761.
- DAC-2005-LuSHZCHH #navigation #network
- Navigating registers in placement for clock network minimization (YL, CCNS, XH, QZ, YC, LH, JH), pp. 176–181.
- Path based buffer insertion (CCNS, CJA, JH, WS), pp. 509–514.
- DAC-2004-AlpertHHQ #flexibility #layout #performance #physics
- Fast and flexible buffer trees that navigate the physical layout environment (CJA, MH, JH, STQ), pp. 24–29.
- DAC-2004-RajaramHM #variability
- Reducing clock skew variability via cross links (AR, JH, RNM), pp. 18–23.
- DAC-2002-SuHSN #network
- Congestion-driven codesign of power and signal networks (HS, JH, SSS, SRN), pp. 64–69.
- DAC-2001-AlpertHSV #resource management
- A Practical Methodology for Early Buffer and Wire Resource Allocation (CJA, JH, SSS, PV), pp. 189–194.
- DAC-1999-HuS #named
- FAR-DS: Full-Plane AWE Routing with Driver Sizing (JH, SSS), pp. 84–89.