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Travelled to:
3 × France
3 × Germany
Collaborated with:
R.Wilcock A.D.Brown S.Ali J.N.Ross R.Rudolf P.Taatizadeh L.Ke T.J.Kazmierski J.Baranowski M.Zwolinski Y.Kiliç J.Kufel S.Hill B.M.Al-Hashimi P.N.Whatmough J.Myers
Talks about:
model (4) behaviour (3) circuit (3) analogu (3) integr (3) configur (2) perform (2) devic (2) vhdl (2) base (2)

Person: Peter R. Wilson

DBLP DBLP: Wilson:Peter_R=

Contributed to:

DATE 20142014
DATE 20122012
DATE 20092009
DATE 20082008
DATE v1 20042004
DATE 20022002

Wrote 7 papers:

DATE-2014-KufelWHAWM #embedded
Clock-modulation based watermark for protection of embedded processors (JK, PRW, SH, BMAH, PNW, JM), pp. 1–6.
DATE-2012-RudolfTWW #automation #configuration management #identification
Automated critical device identification for configurable analogue transistors (RR, PT, RW, PRW), pp. 858–861.
DATE-2009-AliKWW #modelling #optimisation #performance
Improved performance and variation modelling for hierarchical-based optimisation of analogue integrated circuits (SA, LK, RW, PRW), pp. 712–717.
DATE-2009-WilsonW #configuration management #variability
Optimal sizing of configurable devices to reduce variability in integrated circuits (PRW, RW), pp. 1385–1390.
DATE-2008-AliWWB #approach #behaviour #modelling #performance
A New Approach for Combining Yield and Performance in Behavioural Models for Analogue Integrated Circuits (SA, RW, PRW, ADB), pp. 152–157.
DATE-v1-2004-WilsonRBKB #behaviour #modelling #performance
Efficient Mixed-Domain Behavioural Modeling of Ferromagnetic Hysteresis Implemented in VHDL-AMS (PRW, JNR, ADB, TJK, JB), pp. 742–743.
DATE-2002-WilsonRZBK #behaviour #fault #modelling #using
Behavioural Modelling of Operational Amplifier Faults Using VHDL-AMS (PRW, JNR, MZ, ADB, YK), p. 1133.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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