Travelled to:1 × Germany
1 × USA
Collaborated with:C.Visweswariah C.Chen L.Ye F.Chang P.Feldmann N.Ns F.Cano
Talks about:verif (2) level (2) submicron (1) parasit (1) develop (1) effect (1) design (1) analog (1) model (1) digit (1)
Person: Rakesh Chadha
DBLP: Chadha:Rakesh
Contributed to:
1999
1988Wrote 2 papers:
- DATE-1999-YeCFCNC #design #verification
- Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs (LY, FCC, PF, RC, NN, FC), pp. 658–663.
- DAC-1988-VisweswariahCC #development #verification
- Model Development and Verification for High Level Analog Blocks (CV, RC, CFC), pp. 376–382.