Travelled to:1 × Germany
1 × Israel
1 × USA
4 × France
Collaborated with:A.Harsat E.Bolotin I.Cidon A.Kolodny A.Branover R.Kol S.Beer J.Cox T.Chaney D.M.Zar Z.Guz I.Walter K.S.Stevens S.Rotem S.M.Burns J.Cortadella M.Kishinevsky M.Roncken
Talks about:asynchron (3) circuit (2) design (2) fcp (2) methodolog (1) irregular (1) synchron (1) challeng (1) perform (1) network (1)
Person: Ran Ginosar
DBLP: Ginosar:Ran
Contributed to:
2013200720062004
1999
19911990Wrote 7 papers:
- DATE-2013-BeerGCCZ #challenge #metric #simulation
- Metastability challenges for 65nm and beyond: simulation and measurements (SB, RG, JC, TC, DMZ), pp. 1297–1302.
- DATE-2007-BolotinCGK
- Routing table minimization for irregular mesh NoCs (EB, IC, RG, AK), pp. 942–947.
- DATE-2006-GuzWBCGK #capacity #design #performance
- Efficient link capacity and QoS design for network-on-chip (ZG, IW, EB, IC, RG, AK), pp. 9–14.
- DATE-v2-2004-BranoverKG #design
- Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous Ones (AB, RK, RG), pp. 870–877.
- DAC-1999-StevensRBCGKR #performance
- CAD Directions for High Performance Asynchronous Circuits (KSS, SR, SMB, JC, RG, MK, MR), pp. 116–121.
- ICLP-1991-HarsatG #named
- CARMEL-4: The Unify-Spawn Machine for FCP (AH, RG), pp. 840–854.
- CLP-1990-HarsatG90
- An Extended RISC Methodology and its Application to FCP (AH, RG), pp. 67–82.