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Travelled to:
1 × Sweden
2 × USA
Collaborated with:
A.Shrivastava J.Lee A.Rhisheekesan C.Wu Y.Ko Y.Kim K.Lee
Talks about:
cach (3) protect (2) error (2) soft (2) data (2) processor (1) guidelin (1) quantit (1) control (1) analysi (1)

Person: Reiley Jeyapaul

DBLP DBLP: Jeyapaul:Reiley

Contributed to:

DAC 20152015
DAC 20142014
LCTES 20102010

Wrote 3 papers:

DAC-2015-KoJKLS #design #guidelines
Guidelines to design parity protected write-back L1 data cache (YK, RJ, YK, KL, AS), p. 6.
DAC-2014-ShrivastavaRJW #analysis #control flow #fault
Quantitative Analysis of Control Flow Checking Mechanisms for Soft Errors (AS, AR, RJ, CJW), p. 6.
LCTES-2010-ShrivastavaLJ #embedded #equation #fault
Cache vulnerability equations for protecting data in embedded processor caches from soft errors (AS, JL, RJ), pp. 143–152.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.