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Travelled to:
1 × Canada
1 × Ireland
1 × Sweden
4 × Germany
5 × France
5 × USA
Collaborated with:
J.Lee M.Hamzeh S.B.K.Vrudhula Y.Paek K.Bai R.Jeyapaul S.Park N.D.Dutt A.Nicolau E.Earlie T.Rawat Y.Kim N.Dutt S.RajendranRadhika J.Lu J.Boyd H.Sundaram Q.Zhu A.Rhisheekesan C.Wu Y.Kim Y.Ko Y.Kim K.Lee S.K.Mylavarapu S.Choudhuri T.Givargis A.Halambi P.Biswas A.Nicolau
Talks about:
map (6) processor (5) memori (5) cgras (5) data (5) regist (4) bypass (4) error (4) embed (4) soft (4)

Person: Aviral Shrivastava

DBLP DBLP: Shrivastava:Aviral

Contributed to:

DAC 20152015
DATE 20152015
DAC 20142014
DAC 20132013
DATE 20132013
DAC 20122012
DAC 20112011
DATE 20102010
LCTES 20102010
DATE 20092009
LCTES 20092009
DATE 20082008
DATE 20072007
DATE 20062006
LCTES 20062006
DATE 20052005
DATE 20022002

Wrote 22 papers:

DAC-2015-KoJKLS #design #guidelines
Guidelines to design parity protected write-back L1 data cache (YK, RJ, YK, KL, AS), p. 6.
DATE-2015-RajendranRadhika
Path selection based acceleration of conditionals in CGRAs (SR, AS, MH), pp. 121–126.
DATE-2015-RawatS #architecture #concurrent #hybrid #manycore #memory management #thread
Enabling multi-threaded applications on hybrid shared memory manycore architectures (TR, AS), pp. 742–747.
DAC-2014-HamzehSV
Branch-Aware Loop Mapping on CGRAs (MH, AS, SBKV), p. 6.
DAC-2014-ShrivastavaRJW #analysis #control flow #fault
Quantitative Analysis of Control Flow Checking Mechanisms for Soft Errors (AS, AR, RJ, CJW), p. 6.
DAC-2013-HamzehSV #architecture #configuration management #named
REGIMap: register-aware application mapping on coarse-grained reconfigurable architectures (CGRAs) (MH, AS, SBKV), p. 10.
DAC-2013-LuBS #data transformation #multi #named #stack
SSDM: smart stack data management for software managed multicores (SMMs) (JL, KB, AS), p. 8.
DATE-2013-BaiS #architecture #automation #data transformation #manycore #memory management #performance
Automatic and efficient heap data management for limited local memory multicore architectures (KB, AS), pp. 593–598.
DAC-2012-HamzehSV #morphism #named #using
EPIMap: using epimorphism to map applications on CGRAs (MH, AS, SBKV), pp. 1284–1291.
DAC-2011-KimS #data access #memory management #named
CuMAPz: a tool to analyze memory access patterns in CUDA (YK, AS), pp. 128–133.
DATE-2010-BoydSS #detection #process #trade-off
Power-accuracy tradeoffs in human activity transition detection (JB, HS, AS), pp. 1524–1529.
LCTES-2010-KimLSP #memory management #multi
Operation and data mapping for CGRAs with multi-bank memory (YK, JL, AS, YP), pp. 17–26.
LCTES-2010-ShrivastavaLJ #embedded #equation #fault
Cache vulnerability equations for protecting data in embedded processor caches from soft errors (AS, JL, RJ), pp. 143–152.
DATE-2009-LeeS #fault #static analysis
Static analysis to mitigate soft errors in register files (JL, AS), pp. 1367–1372.
DATE-2009-MylavarapuCSLG #file system #named
FSAF: File system aware flash translation layer for NAND Flash Memories (SKM, SC, AS, JL, TG), pp. 399–404.
LCTES-2009-LeeS #compilation #fault #optimisation
A compiler optimization to reduce soft errors in register files (JL, AS), pp. 41–49.
DATE-2008-ParkSP #embedded #execution #using
Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors (SP, AS, YP), pp. 1190–1195.
DATE-2007-ZhuSD #functional #interactive #pipes and filters #validation
Interactive presentation: Functional and timing validation of partially bypassed processor pipelines (QZ, AS, ND), pp. 1164–1169.
DATE-2006-ParkESNDP #automation #embedded #generative #performance
Automatic generation of operation tables for fast exploration of bypasses in embedded processors (SP, EE, AS, AN, ND, YP), pp. 1197–1202.
LCTES-2006-ParkSDNPE #reduction #scheduling
Bypass aware instruction scheduling for register file power reduction (SP, AS, NDD, AN, YP, EE), pp. 173–181.
DATE-2005-ShrivastavaDNE #embedded #framework #named
PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors (AS, NDD, AN, EE), pp. 1264–1269.
DATE-2002-HalambiSBDN #compilation #performance #reduction #using
An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs (AH, AS, PB, NDD, AN), pp. 402–408.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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