BibSLEIGH
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Travelled to:
1 × France
Collaborated with:
N.C.Lourenço N.Horta
Talks about:
floorplan (1) parasit (1) extract (1) layout (1) analog (1) estim (1) size (1) rout (1) awar (1) use (1)

Person: Ricardo Martins

DBLP DBLP: Martins:Ricardo

Contributed to:

DATE 20152015

Wrote 1 papers:

DATE-2015-LourencoMH #using
Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction (NCL, RM, NH), pp. 1156–1161.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.