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Travelled to:
1 × France
1 × Portugal
2 × Germany
Collaborated with:
N.C.Lourenço R.Martins J.M.Pinto R.F.Neves X.Jingnan J.C.Vital R.M.A.e.Silva A.Canelas
Talks about:
analog (3) rout (2) base (2) awar (2) evolutionari (1) electromigr (1) multiport (1) floorplan (1) techniqu (1) structur (1)

Person: Nuno Horta

DBLP DBLP: Horta:Nuno

Contributed to:

DATE 20152015
DATE 20142014
ICEIS v1 20142014
DATE 20012001

Wrote 4 papers:

DATE-2015-LourencoMH #using
Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction (NCL, RM, NH), pp. 1156–1161.
DATE-2014-SilvaLCH #multi
Electromigration-aware and IR-Drop avoidance routing in analog multiport terminal structures (RMAeS, NCL, AC, NH), pp. 1–6.
ICEIS-v1-2014-PintoNH #multi #optimisation
Multi-objective Optimization of Investment Strategies — Based on Evolutionary Computation Techniques, in Volatile Environments (JMP, RFN, NH), pp. 480–488.
DATE-2001-JingnanVH #embedded #library
A Skill-based library for retargetable embedded analog cores (XJ, JCV, NH), pp. 768–769.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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