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Travelled to:
1 × Germany
Collaborated with:
M.Grange D.Pamunuwa H.Tenhunen
Talks about:
interconnect (1) silicon (1) circuit (1) signal (1) integr (1) tsv (1)

Person: Roshan Weerasekera

DBLP DBLP: Weerasekera:Roshan

Contributed to:

DATE 20102010

Wrote 1 papers:

DATE-2010-WeerasekeraGPT #3d #on the
On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits (RW, MG, DP, HT), pp. 1325–1328.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.