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Travelled to:
1 × France
1 × Germany
1 × India
3 × USA
Collaborated with:
A.B.Kahng R.Kumar J.Sartori H.Lee B.Park K.Jeong T.S.Rosing R.D.Strong
Talks about:
power (4) design (3) processor (2) reduct (2) gate (2) methodolog (1) tradeoff (1) recoveri (1) configur (1) arithmet (1)

Person: Seokhyeong Kang

DBLP DBLP: Kang:Seokhyeong

Contributed to:

DAC 20132013
DATE 20132013
DAC 20122012
DATE 20122012
DAC 20102010
HPCA 20102010

Wrote 6 papers:

DAC-2013-KahngKL #reduction
Smart non-default routing for clock power reduction (ABK, SK, HL), p. 7.
DATE-2013-KahngKP #power management #reduction
Active-mode leakage reduction with data-retained power gating (ABK, SK, BP), pp. 1209–1214.
DAC-2012-KahngK #approximate #configuration management #design
Accuracy-configurable adder for approximate arithmetic designs (ABK, SK), pp. 820–825.
DATE-2012-JeongKKRS #memory management #named #power management
MAPG: Memory access power gating (KJ, ABK, SK, TSR, RDS), pp. 1054–1059.
DAC-2010-KahngKKS #design #power management
Recovery-driven design: a power minimization methodology for error-tolerant processor modules (ABK, SK, RK, JS), pp. 825–830.
HPCA-2010-KahngKKS #design #reliability #trade-off
Designing a processor from the ground up to allow voltage/reliability tradeoffs (ABK, SK, RK, JS), pp. 1–11.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.