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Travelled to:
2 × USA
Collaborated with:
Y.Pan G.Memik J.Kong S.W.Chung A.Das G.H.Loh A.N.Choudhary
Talks about:
variat (2) microarchitectur (1) quantifi (1) parametr (1) wordlin (1) process (1) voltag (1) select (1) yield (1) under (1)

Person: Serkan Ozdemir

DBLP DBLP: Ozdemir:Serkan

Contributed to:

DAC 20102010
DAC 20092009

Wrote 2 papers:

DAC-2010-OzdemirPDMLC #3d #architecture #parametricity
Quantifying and coping with parametric variations in 3D-stacked microarchitectures (SO, YP, AD, GM, GHL, ANC), pp. 144–149.
DAC-2009-PanKOMC #process
Selective wordline voltage boosting for caches to manage yield under process variations (YP, JK, SO, GM, SWC), pp. 57–62.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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