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Travelled to:
1 × USA
2 × France
Collaborated with:
H.Choi Y.H.Kim A.R.Newton I.Park C.Kyung J.H.Yi J.Yang B.Kim S.Nam J.Cho S.Seo C.Ryu Y.Kwon D.Lee J.Lee J.Kim H.Yoon J.Kim K.Lee C.Hwang I.Kim J.S.Kim K.Park K.H.Park Y.H.Lee
Talks about:
techniqu (1) synthesi (1) behavior (1) accuraci (1) support (1) multipl (1) develop (1) circuit (1) system (1) switch (1)

Person: Seung Ho Hwang

DBLP DBLP: Hwang:Seung_Ho

Contributed to:

DAC 19981998
DATE 19981998
ED&TC 19971997
DAC 19861986

Wrote 4 papers:

DAC-1998-YangKNCSRKLLKYKLHKKPPLHPK #development #named
MetaCore: An Application Specific DSP Development System (JHY, BWK, SJN, JHC, SWS, CHR, YSK, DHL, JYL, JSK, HDY, JYK, KML, CSH, IHK, JSK, KIP, KHP, YHL, SHH, ICP, CMK), pp. 800–803.
DATE-1998-YiCPHK #behaviour #multi #synthesis
Multiple Behavior Module Synthesis Based on Selective Groupings (JHY, HC, ICP, SHH, CMK), pp. 384–388.
EDTC-1997-ChoiH #estimation
Improving the accuracy of support-set finding method for power estimation of combinational circuits (HC, SHH), pp. 526–530.
DAC-1986-HwangKN #modelling #verification
An accuration delay modeling technique for switch-level timing verification (SHH, YHK, ARN), pp. 227–233.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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