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Collaborated with:
S.H.Hwang A.R.Newton
Talks about:
techniqu (1) switch (1) verif (1) model (1) level (1) delay (1) accur (1) time (1)

Person: Young Hwan Kim

DBLP DBLP: Kim:Young_Hwan

Contributed to:

DAC 19861986

Wrote 1 papers:

DAC-1986-HwangKN #modelling #verification
An accuration delay modeling technique for switch-level timing verification (SHH, YHK, ARN), pp. 227–233.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.