Travelled to:1 × France
1 × Germany
2 × USA
Collaborated with:V.Narayanan C.Wang Y.Chen C.Chiang C.Huang V.Saripalli A.K.Mishra N.Shukla M.Cotter A.Parihar A.Raychowdhury G.Cauwenberghs D.M.Chiarulli S.P.Levitan P.Wong S.Eachempati Y.Xie C.Liu L.Tang
Talks about:transistor (3) electron (3) singl (3) array (3) reconfigur (2) synthesi (2) cmos (2) use (2) heterogen (1) techniqu (1)
Person: Suman Datta
DBLP: Datta:Suman
Contributed to:
2014
201420132011Wrote 6 papers:
- DAC-2014-DattaSCPR
- Neuro Inspired Computing with Coupled Relaxation Oscillators (SD, NS, MC, AP, AR), p. 6.
- DATE-2014-LiuCHWCDN #array #synthesis
- Width minimization in the Single-Electron Transistor array synthesis (CWL, CEC, CYH, CYW, YCC, SD, VN), pp. 1–4.
- DATE-2014-NarayananDCCLW #using #video
- Video analytics using beyond CMOS devices (VN, SD, GC, DMC, SPL, PW), pp. 1–5.
- DATE-2013-ChiangTWHCDN #array #configuration management #on the #order #synthesis #using
- On reconfigurable single-electron transistor arrays synthesis using reordering techniques (CEC, LFT, CYW, CYH, YCC, SD, VN), pp. 1807–1812.
- DAC-2011-ChenEWDXN #array #automation #configuration management
- Automated mapping for reconfigurable single-electron transistor arrays (YCC, SE, CYW, SD, YX, VN), pp. 878–883.
- DAC-2011-SaripalliMDN #energy #hybrid
- An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores (VS, AKM, SD, VN), pp. 729–734.