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Travelled to:
1 × Brazil
1 × France
1 × Germany
2 × USA
Collaborated with:
S.Ramesh A.C.Rajeev S.K.Jha C.J.Langmead J.Millo S.N.Krishna G.K.Narwane A.A.Gadkari A.Yeolekar J.Suresh K.C.Shashidhar M.G.Dixit P.V.Suman P.K.Pandya S.Jiang
Talks about:
embed (3) system (2) model (2) time (2) end (2) architectur (1) constraint (1) automotgen (1) distribut (1) synchron (1)

Person: Swarup Mohalik

DBLP DBLP: Mohalik:Swarup

Contributed to:

DATE 20122012
SPLC 20122012
DATE 20112011
CAV 20082008
DAC 20082008

Wrote 5 papers:

DATE-2012-RajeevMR #architecture #constraints #distributed #embedded #verification
Verifying timing synchronization constraints in distributed embedded architectures (ACR, SM, SR), pp. 200–205.
SPLC-2012-MohalikRMKN
Tracing SPLs precisely and efficiently (SM, SR, JVM, SNK, GKN), pp. 186–195.
DATE-2011-JhaLMR #simulation #statistics #trade-off #verification
When to stop verification?: Statistical trade-off between expected loss and simulation cost (SKJ, CJL, SM, SR), pp. 1309–1314.
CAV-2008-GadkariYSRMS #automation #embedded #generative #named
AutoMOTGen: Automatic Model Oriented Test Generator for Embedded Control Systems (AAG, AY, JS, SR, SM, KCS), pp. 204–208.
DAC-2008-MohalikRDRSPJ #analysis #embedded #latency #model checking #realtime
Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts (SM, ACR, MGD, SR, PVS, PKP, SJ), pp. 296–299.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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