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Travelled to:
1 × USA
Collaborated with:
T.Kim
Talks about:
synthesi (1) testabl (1) design (1) stack (1) clock (1) tree (1) bond (1) pre (1)

Person: Tak-Yung Kim

DBLP DBLP: Kim:Tak=Yung

Contributed to:

DAC 20102010

Wrote 1 papers:

DAC-2010-KimK #3d #design #synthesis #testing
Clock tree synthesis with pre-bond testability for 3D stacked IC designs (TYK, TK), pp. 723–728.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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